HAOUAS Elyes has uploaded this change for review.
sb/intel/ibexpeak: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I212ef304a03d068232f50a71c318e2b468336339
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/pch.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
4 files changed, 22 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40791/1
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index eb75b12..3a66b2c 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -262,8 +262,8 @@
pci_write_config32(dev, 0xd0, reg32);
/* Set Bus Master */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ pci_write_config16(dev, PCI_COMMAND, reg16 | PCI_COMMAND_MASTER);
pci_write_config8(dev, 0x3c, 0x0a); // unused?
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 5f6be1d..e298fba 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -358,6 +358,7 @@
{
struct me_hfs hfs;
u32 reg32;
+ u16 reg16;
mei_base_address = (u32 *)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
@@ -380,10 +381,10 @@
mkhi_end_of_post();
/* Make sure IO is disabled */
- reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND);
- reg32 &= ~(PCI_COMMAND_MASTER |
+ reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND);
+ reg16 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
+ pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16w);
/* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
@@ -475,7 +476,7 @@
{
struct resource *res;
struct mei_csr host;
- u32 reg32;
+ u16 reg16;
/* Find the MMIO base for the ME interface */
res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -486,9 +487,9 @@
mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
/* Clean up status for next message */
read_host_csr(&host);
diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c
index 29c3a76..7e5a025 100644
--- a/src/southbridge/intel/ibexpeak/pch.c
+++ b/src/southbridge/intel/ibexpeak/pch.c
@@ -66,24 +66,24 @@
void pch_enable(struct device *dev)
{
- u32 reg32;
+ u16 reg16;
if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~(PCI_COMMAND_MASTER |
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_write_config16(dev, PCI_COMMAND, reg16);
/* Disable this device if possible */
pch_disable_devfn(dev);
} else {
/* Enable SERR */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_SERR;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
}
}
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 40ba758..0307fc7 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -13,6 +13,7 @@
static void usb_ehci_init(struct device *dev)
{
u32 reg32;
+ u16 reg16;
struct resource *res;
u8 access_cntl;
@@ -30,10 +31,10 @@
pci_write_config32(dev, 0xf4, 0x00808588);
pci_write_config32(dev, 0xfc, 0x301b1728);
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER;
- //reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MASTER;
+ //reg16 |= PCI_COMMAND_SERR;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
access_cntl = pci_read_config8(dev, 0x80);
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