Elyes Haouas has uploaded this change for review.
tree: Use boolean for dmi_power_optimize_disable
Change-Id: Ifbe76bd69d847603345a4a1fa4f41e529634fa92
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
---
M src/mainboard/msi/ms7d25/devicetree.cb
M src/mainboard/msi/ms7e06/devicetree.cb
M src/soc/intel/alderlake/chip.h
3 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/84158/1
diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb
index 1cb6b5d..dd851e1 100644
--- a/src/mainboard/msi/ms7d25/devicetree.cb
+++ b/src/mainboard/msi/ms7d25/devicetree.cb
@@ -83,7 +83,7 @@
}"
register "hybrid_storage_mode" = "true"
- register "dmi_power_optimize_disable" = "1"
+ register "dmi_power_optimize_disable" = "true"
# FIVR configuration
register "fivr_rfi_frequency" = "1394"
diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb
index a613980..31ba6a3 100644
--- a/src/mainboard/msi/ms7e06/devicetree.cb
+++ b/src/mainboard/msi/ms7e06/devicetree.cb
@@ -13,7 +13,7 @@
register "pmc_gpe0_dw2" = "GPD"
register "hybrid_storage_mode" = "true"
- register "dmi_power_optimize_disable" = "1"
+ register "dmi_power_optimize_disable" = "true"
# FIVR configuration
register "fivr_rfi_frequency" = "1394"
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index c8005de..7e520bb 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -575,8 +575,8 @@
uint8_t cpu_ratio_override;
/*
- * Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
- * Default 0. Setting this to 1 disables the DMI Power Optimizer.
+ * Enable/Disable DMI Power Optimizer on PCH side.
+ * Default is "false".
*/
bool dmi_power_optimize_disable;
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