[coreboot-gerrit] [XS] Change in coreboot[master]: mb/system76/tgl-u: Enable reporting CPU C10 state over eSPI

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73689?usp=email )

Change subject: mb/system76/tgl-u: Enable reporting CPU C10 state over eSPI
......................................................................

mb/system76/tgl-u: Enable reporting CPU C10 state over eSPI

This allows the EC to detect C10 using eSPI instead of a dedicated pin.

Change-Id: I58c03d91466b869d53c9ee2cbbe50adc32539494
Signed-off-by: Jeremy Soller 
Signed-off-by: Tim Crawford 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73689
Tested-by: build bot (Jenkins) 
---
M src/mainboard/system76/tgl-u/variants/darp7/ramstage.c
M src/mainboard/system76/tgl-u/variants/galp5/ramstage.c
M src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c
3 files changed, 9 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Jeremy Soller: Looks good to me, approved

diff --git a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c
index a60587d..2b64f9f 100644
--- a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c
+++ b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c
@@ -12,4 +12,7 @@
    // IOM config
    params->PchUsbOverCurrentEnable = 0;
    params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+
+	// Enable reporting CPU C10 state over eSPI
+	params->PchEspiHostC10ReportEnable = 1;
 }
diff --git a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c
index a60587d..2b64f9f 100644
--- a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c
+++ b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c
@@ -12,4 +12,7 @@
    // IOM config
    params->PchUsbOverCurrentEnable = 0;
    params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+
+	// Enable reporting CPU C10 state over eSPI
+	params->PchEspiHostC10ReportEnable = 1;
 }
diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c
index 2064836..8b80740 100644
--- a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c
+++ b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c
@@ -12,4 +12,7 @@
    // IOM config
    params->PchUsbOverCurrentEnable = 0;
    params->PortResetMessageEnable[2] = 1; // J_TYPEC1
+
+	// Enable reporting CPU C10 state over eSPI
+	params->PchEspiHostC10ReportEnable = 1;
 }