Patrick Georgi submitted this change.
mb/intel/shadowmountain: Add Cr50 support
This patch includes changes to add Cr50 support over GSPI0.
BUG=b:175579964
TEST=Verify TPM init is done and boots to kernel
Change-Id: I33f7427d1675190f65acf14679be93546e6db69a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51086
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/intel/shadowmountain/Kconfig
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
index a8f7bf5..e42160f 100644
--- a/src/mainboard/intel/shadowmountain/Kconfig
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -20,6 +20,8 @@
select HAVE_SPD_IN_CBFS
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_SPI_TPM_CR50
+ select MAINBOARD_HAS_TPM2
select PCIEXP_HOTPLUG
select SOC_INTEL_ALDERLAKE
select SOC_INTEL_CSE_LITE_SKU
@@ -34,7 +36,6 @@
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select VBOOT_LID_SWITCH
- select VBOOT_MOCK_SECDATA
select HAS_RECOVERY_MRC_CACHE
config DIMM_SPD_SIZE
@@ -69,4 +70,11 @@
hex
default 0x1c000000 # 448 MiB
+config DRIVER_TPM_SPI_BUS
+ default 0x1
+
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 3 # GPE0_DW0_3 (GPP_C3)
+
endif # BOARD_INTEL_SHADOWMOUNTAIN
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 98f6400..8b31784 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -311,7 +311,14 @@
device pci 1d.3 off end # RP12
device pci 1e.0 on end # UART0
device pci 1e.1 off end # UART1
- device pci 1e.2 on end # GSPI0
+ device pci 1e.2 on
+ chip drivers/spi/acpi
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "compat_string" = ""google,cr50""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C3_IRQ)"
+ device spi 0 on end
+ end
+ end # GSPI0
device pci 1e.3 off end # GSPI1
device pci 1f.0 on
chip ec/google/chromeec
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