[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22839

Change subject: soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS
......................................................................

soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS

TEST=System is able to power on after reconnecting power system.

Change-Id: Ic707164a576ffb25418eb6553843cd8edc608800
Signed-off-by: Subrata Banik 
---
M src/soc/intel/skylake/pmc.c
1 file changed, 42 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22839/1

diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index 91b319c..5f3ef2b 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */

+#include <bootstate.h>
 #include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
@@ -73,9 +74,24 @@
    REG_SCRIPT_END
 };

+/*
+ * Determines what state to go to when power is reapplied
+ * after a power failure (G3 State)
+ */
+static void pmc_set_afterg3(struct device *dev, int s5pwr)
+{
+	uint8_t reg8;
+
+	reg8 = pci_read_config8(PCH_DEV_PMC, GEN_PMCON_B);
+	if (s5pwr == MAINBOARD_POWER_ON)
+		reg8 &= ~1;
+	else
+		reg8 |= 1;
+	pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8);
+}
+
 static void pch_power_options(struct device *dev)
 {
-	u16 reg16;
    const char *state;

/* Get the chip configuration */
@@ -91,25 +107,20 @@
    /*TODO: cmos_layout.bin need to verify; cause wrong CMOS setup*/
    //get_option(&pwr_on, "power_on_after_fail");
    pwr_on = MAINBOARD_POWER_ON;
-	reg16 = pci_read_config16(dev, GEN_PMCON_B);
-	reg16 &= 0xfffe;
    switch (pwr_on) {
    case MAINBOARD_POWER_OFF:
-		reg16 |= 1;
    	state = "off";
    	break;
    case MAINBOARD_POWER_ON:
-		reg16 &= ~1;
    	state = "on";
    	break;
    case MAINBOARD_POWER_KEEP:
-		reg16 &= ~1;
    	state = "state keep";
    	break;
    default:
    	state = "undefined";
    }
-	pci_write_config16(dev, GEN_PMCON_B, reg16);
+	pmc_set_afterg3(dev, pwr_on);
    printk(BIOS_INFO, "Set power %s after power failure.\n", state);

/* Set up GPE configuration. */
@@ -178,4 +189,28 @@
    /* Clear registers that contain write-1-to-clear bits. */
    reg_script_run_on_dev(dev, pmc_write1_to_clear_script);
 }
+
+/*
+ * Set PMC register to know which state system should be after
+ * power reapplied
+ */
+void pmc_soc_restore_power_failiure(void)
+{
+	pmc_set_afterg3(PCH_DEV_PMC, MAINBOARD_POWER_ON);
+}
+
+static void pm1_enable_pwrbtn_smi(void *unused)
+{
+	/*
+	 * Enable power button SMI only before jumping to payload. This ensures
+	 * that:
+	 * 1. Power button SMI is enabled only after coreboot is done.
+	 * 2. On resume path, power button SMI is not enabled and thus avoids
+	 * any shutdowns because of power button presses due to power button
+	 * press in resume path.
+	 */
+	pmc_update_pm1_enable(PWRBTN_EN);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
 #endif