Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Subrata Banik, Arthur Heymans, Michael Niewöhner, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35985
to look at the new patch set (#13).
Change subject: intel/skylake: Implement PCIe RP devicetree update based on DID ......................................................................
intel/skylake: Implement PCIe RP devicetree update based on DID
The old code stumbled when the whole first group of root ports was disabled and also made the (sometimes wrong) assumption that FSP would only hide function 0 if we explicitly told it to disable it.
This, new implementation acts solely on device IDs read with pci_s_read_config16(). In a first round, we scan all possible DEVFNs and store which root port has that DEVFN now. Then, we walk through the devicetree that still only knows devices that were originally mentioned in `devicetree.cb`, and update the device paths.
In theory, this should work no matter who (coreboot vs. FSP) reordered the root ports and no matter what rules were used.
Change-Id: Ib17d2b6fd34608603db3936d638bdf5acb46d717 Signed-off-by: Nico Huber nico.h@gmx.de --- A src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/common/block/pcie/Makefile.inc A src/soc/intel/common/block/pcie/pcie_rp.c M src/soc/intel/skylake/chip.c 4 files changed, 283 insertions(+), 115 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/35985/13