Angel Pons submitted this change.
cpu/intel/haswell/haswell.h: Align with Broadwell
Sort MSR definitions, move MCHBAR registers to northbridge and relocate
C-state latency macros into the header.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46914
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/cpu/intel/haswell/haswell.h
M src/cpu/intel/haswell/haswell_init.c
M src/northbridge/intel/haswell/registers/mchbar.h
3 files changed, 52 insertions(+), 56 deletions(-)
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index deadbc5..284ff01 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -21,22 +21,29 @@
#define CPU_BCLK 100
#define MSR_CORE_THREAD_COUNT 0x35
-#define MSR_FEATURE_CONFIG 0x13c
-#define MSR_FLEX_RATIO 0x194
-#define FLEX_RATIO_LOCK (1 << 20)
-#define FLEX_RATIO_EN (1 << 16)
-#define MSR_TEMPERATURE_TARGET 0x1a2
-#define MSR_LT_LOCK_MEMORY 0x2e7
-
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
-
+#define MSR_FEATURE_CONFIG 0x13c
+#define SMM_MCA_CAP_MSR 0x17d
+#define SMM_CPU_SVRSTR_BIT 57
+#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
+#define MSR_FLEX_RATIO 0x194
+#define FLEX_RATIO_LOCK (1 << 20)
+#define FLEX_RATIO_EN (1 << 16)
+#define MSR_TEMPERATURE_TARGET 0x1a2
#define MSR_MISC_PWR_MGMT 0x1aa
#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
#define MSR_TURBO_RATIO_LIMIT 0x1ad
+#define MSR_PRMRR_PHYS_BASE 0x1f4
+#define MSR_PRMRR_PHYS_MASK 0x1f5
#define MSR_POWER_CTL 0x1fc
+#define MSR_LT_LOCK_MEMORY 0x2e7
+#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
+#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
+#define SMM_FEATURE_CONTROL_MSR 0x4e0
+#define SMM_CPU_SAVE_EN (1 << 1)
#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a
#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b
@@ -53,7 +60,7 @@
#define IRTL_33554432_NS (5 << 10)
#define IRTL_RESPONSE_MASK (0x3ff)
-/* long duration in low dword, short duration in high dword */
+/* Long duration in low dword, short duration in high dword */
#define MSR_PKG_POWER_LIMIT 0x610
#define PKG_POWER_LIMIT_MASK 0x7fff
#define PKG_POWER_LIMIT_EN (1 << 15)
@@ -76,18 +83,6 @@
#define MSR_CONFIG_TDP_CONTROL 0x64b
#define MSR_TURBO_ACTIVATION_RATIO 0x64c
-#define SMM_MCA_CAP_MSR 0x17d
-#define SMM_CPU_SVRSTR_BIT 57
-#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
-
-#define MSR_PRMRR_PHYS_BASE 0x1f4
-#define MSR_PRMRR_PHYS_MASK 0x1f5
-#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
-#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
-
-#define SMM_FEATURE_CONTROL_MSR 0x4e0
-#define SMM_CPU_SAVE_EN (1 << 1)
-
/* SMM save state MSRs */
#define SMBASE_MSR 0xc20
#define IEDBASE_MSR 0xc22
@@ -96,33 +91,26 @@
#define SMRR_SUPPORTED (1 << 11)
#define PRMRR_SUPPORTED (1 << 12)
+/* Intel suggested latency times in units of 1024ns. */
+#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
+#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
+#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
+#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
+#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
+#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
+
+#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
+ (((1 << ((base) * 5)) * (limit)) / 1000)
+#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
+ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
+ (IRTL_1024_NS >> 10))
+
/* P-state configuration */
#define PSS_MAX_ENTRIES 8
#define PSS_RATIO_STEP 2
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
-/* PCODE MMIO communications live in the MCHBAR. */
-#define BIOS_MAILBOX_INTERFACE 0x5da4
-#define MAILBOX_RUN_BUSY (1 << 31)
-#define MAILBOX_BIOS_CMD_READ_PCS 1
-#define MAILBOX_BIOS_CMD_WRITE_PCS 2
-#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509
-#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909
-#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa
-#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb
-/* Errors are returned back in bits 7:0. */
-#define MAILBOX_BIOS_ERROR_NONE 0
-#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
-#define MAILBOX_BIOS_ERROR_TIMEOUT 2
-#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3
-#define MAILBOX_BIOS_ERROR_RESERVED 4
-#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5
-#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6
-#define MAILBOX_BIOS_ERROR_VR_ERROR 7
-/* Data is passed through bits 31:0 of the data register. */
-#define BIOS_MAILBOX_DATA 0x5da0
-
/* Sanity check config options. */
#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE))
# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)"
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 86a9053..44bbbfd 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -20,20 +20,6 @@
#include "haswell.h"
#include "chip.h"
-/* Intel suggested latency times in units of 1024ns. */
-#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
-#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
-#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
-#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
-#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
-#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
-
-#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
- (((1 << ((base)*5)) * (limit)) / 1000)
-#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
- C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
- (IRTL_1024_NS >> 10))
-
/*
* List of supported C-states in this processor. Only the ULT parts support C8,
* C9, and C10.
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 97ae433..4bdb49a 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -34,6 +34,28 @@
#define MCH_DDR_POWER_LIMIT_HI 0x58e4
#define SSKPD 0x5d10 /* 64-bit scratchpad register */
+
+/* PCODE MMIO communications live in the MCHBAR */
+#define BIOS_MAILBOX_DATA 0x5da0
+
+#define BIOS_MAILBOX_INTERFACE 0x5da4
+#define MAILBOX_RUN_BUSY (1 << 31)
+#define MAILBOX_BIOS_CMD_READ_PCS 1
+#define MAILBOX_BIOS_CMD_WRITE_PCS 2
+#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509
+#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909
+#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa
+#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb
+/* Errors are returned back in bits 7:0 */
+#define MAILBOX_BIOS_ERROR_NONE 0
+#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
+#define MAILBOX_BIOS_ERROR_TIMEOUT 2
+#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3
+#define MAILBOX_BIOS_ERROR_RESERVED 4
+#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5
+#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6
+#define MAILBOX_BIOS_ERROR_VR_ERROR 7
+
#define BIOS_RESET_CPL 0x5da8 /* 8-bit */
#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */
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