Subrata Banik submitted this change.

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Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
mb/*/jslrvp/dedede: Remove hardcoding of BSP APIC ID

coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.

As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.

BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.

Change-Id: I726d70b4ffc35a28a654abbd20c866f1410e1aee
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index cb5321c..38b1da27 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -27,9 +27,7 @@
end

chip soc/intel/jasperlake
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+ device cpu_cluster 0 on end

# GPE configuration
# Note that GPE events called out in ASL code rely on this
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index 34f9eae..262e27df 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -1,8 +1,6 @@
chip soc/intel/jasperlake

- device cpu_cluster 0 on
- device lapic 0 on end
- end
+ device cpu_cluster 0 on end

# GPE configuration
# Note that GPE events called out in ASL code rely on this

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I726d70b4ffc35a28a654abbd20c866f1410e1aee
Gerrit-Change-Number: 56759
Gerrit-PatchSet: 5
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub@google.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Simon Yang <simon1.yang@intel.com>
Gerrit-MessageType: merged