Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu.
Shuo Liu uploaded patch set #3 to this change.
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Verified+1 by build bot (Jenkins)
soc/intel/xeon_sp: Add soc_add_dram_resources
SoC specific DRAM resource, e.g. 4GB above DRAM memory map, CXL,
et al, are different across SoC generations. This patch separates
the codes so that different SoC generations could have different
implementations.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie15b11e1f4cdc861324286b1397f9c5e431b74ab
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
---
M src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/uncore.c
3 files changed, 87 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/81958/3
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ie15b11e1f4cdc861324286b1397f9c5e431b74ab
Gerrit-Change-Number: 81958
Gerrit-PatchSet: 3
Gerrit-Owner: Shuo Liu <shuo.liu@intel.com>
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