Paul Menzel uploaded patch set #4 to this change.

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mb/asus/f2a85-m_pro: Enable PCIe bridge 00:15.2 in AGESA

Currently, the PCIe bridge 00:15.2 is not detected by coreboot, causing
the connected network device also to be missing.

This is caused, by not configuring the third of the four PCIe General
Purpose Ports (GPP) of the AMD Fusion Controller Hub (FCH), which can be
exposed as one to four PCIe devices.

So, enable it in AGESA but disable enumeration in coreboot. Otherwise,
the serial console stops working in romstage after

    […]
    PCI: 00:15.1 bridge ctrl <- 0013
    PCI: 00:15.1 cmd <- 06
    PCI: 00:15.2 bridge ctrl <- 0013
    PCI: 00:15.2 cmd <- 07

and the system hangs in the payload (SeaBIOS banner is shown on VGA
attached monitor).

TEST=Serial console and payload works, and Linux 5.10-rc2 configures
     PCIe bridge. Output of `lspci -t`:

    -[0000:00]-+-00.0
               +-00.2
               +-01.0
               +-01.1
               +-10.0
               +-10.1
               +-11.0
               +-12.0
               +-12.2
               +-13.0
               +-13.2
               +-14.0
               +-14.2
               +-14.3
               +-14.4-[01]--
               +-14.5
               +-15.0-[02]--
               +-15.1-[03]----00.0
               +-15.2-[04]----00.0
               +-18.0
               +-18.1
               +-18.2
               +-18.3
               +-18.4
               \-18.5

Change-Id: Ia1d60a212b0d249c7d8b3f8ec16baf5e93c985da
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
---
M src/mainboard/asus/f2a85-m/buildOpts.c
M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb
2 files changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/46527/4

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