Nick Chen has uploaded this change for review.
mb/google/volteer/variants/eldrid: add memory.c for ddr4 support
Add new memory.c to support DDR4 memory types.
Use the new meminit_ddr() and variant_memory_sku() for eldrid variant code
on memory.c
BUG=b:161772961
TEST='emerge-volteer coreboot chromeos-bootimage' and verify that volteer
can boots. NOTE that tests the ddr4 side of the implementation.
Change-Id: I2c7b30093a8d85bac5aba5b83768af5eb36c4f70
---
A src/mainboard/google/volteer/variants/eldrid/Makefile.inc
A src/mainboard/google/volteer/variants/eldrid/gpio.c
A src/mainboard/google/volteer/variants/eldrid/memory.c
M src/mainboard/google/volteer/variants/eldrid/overridetree.cb
4 files changed, 523 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/44632/1
diff --git a/src/mainboard/google/volteer/variants/eldrid/Makefile.inc b/src/mainboard/google/volteer/variants/eldrid/Makefile.inc
new file mode 100644
index 0000000..343c7db
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/eldrid/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += memory.c
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c
new file mode 100644
index 0000000..0ff354e
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c
@@ -0,0 +1,298 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+ /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
+ PAD_CFG_GPO(GPP_A7, 1, DEEP),
+ /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
+ PAD_CFG_GPO(GPP_A8, 0, DEEP),
+ /* A10 : I2S2_RXD ==> EN_SPKR_PA */
+ PAD_CFG_GPO(GPP_A10, 1, DEEP),
+ /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
+ PAD_CFG_GPO(GPP_A13, 1, DEEP),
+ /* A15 : USB_OC2# ==> NC */
+ PAD_NC(GPP_A15, NONE),
+ /* A16 : USB_OC3# ==> USB_C0_OC_ODL */
+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+ /* A18 : DDSP_HPDB ==> NC */
+ PAD_NC(GPP_A18, NONE),
+ /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
+ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+ /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
+ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+ /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
+ PAD_CFG_GPO(GPP_A21, 1, DEEP),
+ /* A22 : DDPC_CTRLDATA ==> NC */
+ PAD_NC(GPP_A22, NONE),
+ /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
+ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
+
+ /* B2 : VRALERT# ==> EN_PP3300_SSD */
+ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+ /* B3 : CPU_GP2 ==> NC */
+ PAD_NC(GPP_B3, NONE),
+ /* B5 : ISH_I2C0_CVF_SDA ==> NC */
+ PAD_NC(GPP_B5, NONE),
+ /* B6 : ISH_I2C0_CVF_SCL ==> NC */
+ PAD_NC(GPP_B6, NONE),
+ /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+ /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+ /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+ /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+ /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
+ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+ /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
+ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+ /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
+ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+
+ /* C0 : SMBCLK ==> EN_PP3300_WLAN */
+ PAD_CFG_GPO(GPP_C0, 1, DEEP),
+ /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP_0 */
+ PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+ /* C7 : SML1DATA ==> NC */
+ PAD_NC(GPP_C7, NONE),
+ /* C10 : UART0_RTS# ==> USI_RST_L */
+ PAD_CFG_GPO(GPP_C10, 0, DEEP),
+ /* C13 : UART1_TXD ==> NC */
+ PAD_NC(GPP_C13, NONE),
+ /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+ /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+ /* C20 : UART2_RXD ==> FPMCU_INT_L */
+ /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */
+ PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL),
+ /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+ PAD_CFG_GPO(GPP_C22, 0, DEEP),
+ /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
+ PAD_CFG_GPO(GPP_C23, 1, DEEP),
+
+ /* D1 : ISH_GP1 ==> NC */
+ PAD_NC(GPP_D1, NONE),
+ /* D2 : ISH_GP2 ==> NC */
+ PAD_NC(GPP_D2, NONE),
+ /* D3 : ISH_GP3 ==> NC */
+ PAD_NC(GPP_D3, NONE),
+ /* D4 : IMGCLKOUT0 ==> NC */
+ PAD_NC(GPP_D4, NONE),
+ /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+ /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+ /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */
+ PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+ /* D13 : ISH_UART0_RXD ==> NC */
+ PAD_NC(GPP_D13, NONE),
+ /* D14 : ISH_UART0_TXD ==> NC */
+ PAD_NC(GPP_D14, NONE),
+ /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
+ PAD_CFG_GPO(GPP_D16, 1, DEEP),
+ /* D17 : ISH_GP4 ==> EN_FCAM_PWR */
+ PAD_CFG_GPO(GPP_D17, 1, DEEP),
+ /* D18 : ISH_GP5 ==> NC */
+ PAD_NC(GPP_D18, NONE),
+
+ /* E0 : SATAXPCIE0 ==> USB_C1_RT_PWR_EN */
+ PAD_CFG_GPO(GPP_E0, 1, DEEP),
+ /* E1 : SPI1_IO2 ==> NC */
+ PAD_NC(GPP_E1, NONE),
+ /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+ /* E3 : CPU_GP0 ==> USI_REPORT_EN */
+ PAD_CFG_GPO(GPP_E3, 1, DEEP),
+ /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+ /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */
+ PAD_CFG_GPI(GPP_E6, NONE, DEEP),
+ /* E7 : CPU_GP1 ==> USI_INT */
+ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
+ /* E8 : SPI1_CS1# ==> SLP_S0IX */
+ PAD_CFG_GPO(GPP_E8, 0, DEEP),
+ /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */
+ PAD_CFG_GPO(GPP_E10, 1, DEEP),
+ /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+ /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */
+ PAD_CFG_GPO(GPP_E13, 1, DEEP),
+ /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
+ PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
+ /* E16 : ISH_GP7 ==> NC */
+ PAD_NC(GPP_E16, NONE),
+ /* E17 : THC0_SPI1_INT# ==> NC */
+ PAD_NC(GPP_E17, NONE),
+ /* E20 : DDP2_CTRLCLK ==> NC */
+ PAD_NC(GPP_E20, NONE),
+ /* E21 : DDP2_CTRLDATA ==> NC */
+ PAD_NC(GPP_E21, NONE),
+ /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */
+ PAD_CFG_GPO(GPP_E22, 1, DEEP),
+ /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */
+ PAD_CFG_GPO(GPP_E23, 1, DEEP),
+
+ /* F6 : CNV_PA_BLANKING ==> NC */
+ PAD_NC(GPP_F6, NONE),
+ /* F7 : GPPF7_STRAP ==> GPP_F7_STRAP */
+ PAD_CFG_GPI(GPP_F7, NONE, DEEP),
+ /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */
+ PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH),
+ /* F10 : GPPF10_STRAP ==> GPP_F10_STRAP */
+ PAD_CFG_GPI(GPP_F10, NONE, DEEP),
+ /* F11 : THC1_SPI2_CLK ==> NC */
+ PAD_NC(GPP_F11, NONE),
+ /* F12 : GSXDOUT ==> NC */
+ PAD_NC(GPP_F12, NONE),
+ /* F13 : GSXDOUT ==> WiFi_DISABLE_L */
+ PAD_CFG_GPO(GPP_F13, 1, DEEP),
+ /* F14 : GSXDIN ==> NC */
+ PAD_NC(GPP_F14, NONE),
+ /* F15 : GSXSRESET# ==> NC */
+ PAD_NC(GPP_F15, NONE),
+ /* F16 : GSXCLK ==> NC */
+ PAD_NC(GPP_F16, NONE),
+ /* F17 : THC1_SPI2_RST# ==> NC */
+ PAD_NC(GPP_F17, NONE),
+ /* F18 : THC1_SPI2_INT# ==> NC */
+ PAD_NC(GPP_F18, NONE),
+ /* F19 : SRCCLKREQ6# ==> NC */
+ PAD_NC(GPP_F19, NONE),
+
+ /* H0 : GPPH0_BOOT_STRAP1 */
+ PAD_CFG_GPI(GPP_H0, NONE, DEEP),
+ /* H1 : GPPH1_BOOT_STRAP2 */
+ PAD_CFG_GPI(GPP_H1, NONE, DEEP),
+ /* H2 : GPPH2_BOOT_STRAP3 */
+ PAD_CFG_GPI(GPP_H2, NONE, DEEP),
+ /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
+ PAD_CFG_GPO(GPP_H3, 1, DEEP),
+ /* H4 : I2C2_SDA ==> NC */
+ PAD_NC(GPP_H4, NONE),
+ /* H5 : I2C2_SCL ==> NC */
+ PAD_NC(GPP_H5, NONE),
+ /* H6 : I2C3_SDA ==> NC */
+ PAD_NC(GPP_H6, NONE),
+ /* H7 : I2C3_SCL ==> NC */
+ PAD_NC(GPP_H7, NONE),
+ /* H8 : I2C4_SDA ==> NC */
+ PAD_NC(GPP_H8, NONE),
+ /* H9 : I2C4_SCL ==> NC */
+ PAD_NC(GPP_H9, NONE),
+ /* H10 : SRCCLKREQ4# ==> NC */
+ PAD_NC(GPP_H10, NONE),
+ /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
+ PAD_CFG_GPO(GPP_H11, 1, DEEP),
+ /* H12 : M2_SKT2_CFG0 ==> NC */
+ PAD_NC(GPP_H12, NONE),
+ /* H13 : M2_SKT2_CFG1 # ==> NC */
+ PAD_NC(GPP_H13, NONE),
+ /* H14 : M2_SKT2_CFG2 # ==> NC */
+ PAD_NC(GPP_H14, NONE),
+ /* H15 : M2_SKT2_CFG3 # ==> NC */
+ PAD_NC(GPP_H15, NONE),
+ /* H16 : DDPB_CTRLCLK ==> NC */
+ PAD_NC(GPP_H16, NONE),
+ /* H17 : DDPB_CTRLDATA ==> NC */
+ PAD_NC(GPP_H17, NONE),
+ /* H19 : TIME_SYNC0 ==> NC */
+ PAD_NC(GPP_H19, NONE),
+ /* H20 : IMGCLKOUT1 ==> NC */
+ PAD_NC(GPP_H20, NONE),
+ /* H21 : IMGCLKOUT2 ==> NC */
+ PAD_NC(GPP_H21, NONE),
+ /* H22 : IMGCLKOUT3 ==> NC */
+ PAD_NC(GPP_H22, NONE),
+
+ /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+ /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
+ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+ /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
+ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+ /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
+ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+ /* R5 : HDA_SDI1 ==> NC */
+ PAD_NC(GPP_R5, NONE),
+ /* R6 : I2S1_TXD ==> I2S1_PCH_TX_SPKR_RX_R */
+ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+ /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM_R */
+ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+
+ /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK_R */
+ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
+ /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA_R */
+ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
+ /* S2 : SNDW1_CLK ==> NC */
+ PAD_NC(GPP_S2, NONE),
+ /* S3 : SNDW1_DATA ==> NC */
+ PAD_NC(GPP_S3, NONE),
+ /* S4 : SNDW2_CLK ==> PCH_DMIC_CAM_SCL_R */
+ PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
+ /* S5 : SNDW2_DATA ==> PCH_DMIC_CAM_SDA_R */
+ PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
+ /* S6 : SNDW3_CLK ==> NC */
+ PAD_NC(GPP_S6, NONE),
+ /* S7 : SNDW3_DATA ==> NC */
+ PAD_NC(GPP_S7, NONE),
+
+ /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
+ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+ /* A17 : DDSP_HPDC ==> MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+
+ /* B11 : PMCALERT# ==> PCH_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+ /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
+ PAD_CFG_GPI(GPP_B18, NONE, DEEP),
+
+ /* C0 : SMBCLK ==> EN_PP3300_WLAN */
+ PAD_CFG_GPO(GPP_C0, 1, DEEP),
+ /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+ /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+ PAD_CFG_GPO(GPP_C22, 0, DEEP),
+
+ /* E12 : SPI1_MISO_IO1 ==> NC */
+ PAD_NC(GPP_E12, NONE),
+
+ /* F11 : THC1_SPI2_CLK ==> NC */
+ PAD_NC(GPP_F11, NONE),
+
+ /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
+ PAD_CFG_GPO(GPP_H11, 1, DEEP),
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(override_gpio_table);
+ return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
diff --git a/src/mainboard/google/volteer/variants/eldrid/memory.c b/src/mainboard/google/volteer/variants/eldrid/memory.c
new file mode 100644
index 0000000..3291d5d
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/eldrid/memory.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+static const struct mb_ddr4_cfg eldrid_memcfg = {
+};
+
+static const struct ddr_memory_cfg baseboard_memcfg = {
+ .mem_type = MEMTYPE_DDR4,
+ .ddr4_cfg = &eldrid_memcfg
+};
+
+const struct ddr_memory_cfg *variant_memory_params(void)
+{
+ return &baseboard_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+ gpio_t spd_gpios[] = {
+ GPIO_MEM_CONFIG_3,
+ GPIO_MEM_CONFIG_2,
+ GPIO_MEM_CONFIG_1,
+ GPIO_MEM_CONFIG_0,
+ };
+
+ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
index 89026b8..99d883b 100644
--- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
@@ -3,8 +3,194 @@
register "TcssAuxOri" = "1"
register "IomTypeCPortPadCfg[0]" = "0x090E000A"
register "IomTypeCPortPadCfg[1]" = "0x090E000D"
-
+ register "SaGv" = "SaGv_Disabled"
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| GSPI1 | Fingerprint MCU |
+ #| I2C0 | Audio |
+ #| I2C1 | Touchscreen |
+ #| I2C2 | WLAN, SAR0 |
+ #| I2C3 | Camera, SAR1 |
+ #| I2C5 | Trackpad |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 163,
+ .scl_hcnt = 75,
+ .sda_hold = 36,
+ },
+ },
+ }"
device domain 0 on
+ device pci 04.0 off
+ end
+ device pci 15.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5682""
+ register "name" = ""RT58""
+ register "desc" = ""Headset Codec""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)"
+ # Set the jd_src to RT5668_JD1 for jack detection
+ register "property_count" = "1"
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on
+ probe AUDIO MAX98357_ALC5682I_I2S
+ probe AUDIO MAX98373_ALC5682I_I2S
+ end
+ end
+ chip drivers/i2c/max98373
+ register "vmon_slot_no" = "0"
+ register "imon_slot_no" = "1"
+ register "uid" = "0"
+ register "desc" = ""Right Speaker Amp""
+ register "name" = ""MAXR""
+ device i2c 31 on
+ probe AUDIO MAX98373_ALC5682I_I2S
+ end
+ end
+ chip drivers/i2c/max98373
+ register "vmon_slot_no" = "2"
+ register "imon_slot_no" = "3"
+ register "uid" = "1"
+ register "desc" = ""Left Speaker Amp""
+ register "name" = ""MAXL""
+ device i2c 32 on
+ probe AUDIO MAX98373_ALC5682I_I2S
+ end
+ end
+ end
+ device pci 15.1 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""GDIX0000""
+ register "generic.desc" = ""Goodix Touchscreen""
+ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+ register "generic.probed" = "1"
+ register "generic.reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+ register "generic.reset_delay_ms" = "120"
+ register "generic.reset_off_delay_ms" = "3"
+ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
+ register "generic.enable_delay_ms" = "12"
+ register "generic.has_power_resource" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 14 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""ELAN90FC""
+ register "generic.desc" = ""ELAN Touchscreen""
+ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+ register "generic.probed" = "1"
+ register "generic.reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
+ register "generic.reset_delay_ms" = "20"
+ register "generic.has_power_resource" = "1"
+ register "generic.disable_gpio_export_in_crs" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 10 on end
+ end
+ end # I2C1 0xA0E9
+ device pci 19.1 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
+ register "wake" = "GPE0_DW2_15"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
+ end # I2C5 0xA0C6
+ device pci 1f.3 on
+ chip drivers/generic/max98357a
+ register "hid" = ""MX98357A""
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
+ register "sdmode_delay" = "5"
+ device generic 0 on
+ probe AUDIO MAX98357_ALC5682I_I2S
+ end
+ end
+ chip drivers/intel/soundwire
+ device generic 0 on
+ probe AUDIO MAX98373_ALC5682_SNDW
+ chip drivers/soundwire/alc5682
+ # SoundWire Link 0 ID 1
+ register "desc" = ""Headset Codec""
+ device generic 0.1 on end
+ end
+ chip drivers/soundwire/max98373
+ # SoundWire Link 1 ID 3
+ register "desc" = ""Left Speaker Amp""
+ device generic 1.3 on end
+ end
+ chip drivers/soundwire/max98373
+ # SoundWire Link 1 ID 7
+ register "desc" = ""Right Speaker Amp""
+ device generic 1.7 on end
+ end
+ end
+ end
+ end
+ device pci 1f.2 hidden
+ # The pmc_mux chip driver is a placeholder for the
+ # PMC.MUX device in the ACPI hierarchy.
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "9"
+ register "usb3_port_number" = "1"
+ # SBU & HSL follow CC
+ device generic 0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "4"
+ register "usb3_port_number" = "2"
+ # SBU is fixed, HSL follows CC
+ register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+ device generic 1 on
+ probe DB_USB USB4_GEN2
+ probe DB_USB USB3_ACTIVE
+ probe DB_USB USB4_GEN3
+ probe DB_USB USB3_NO_A
+ end
+ end
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "4"
+ register "usb3_port_number" = "2"
+ # SBU & HSL follow CC
+ device generic 1 on
+ probe DB_USB USB3_PASSIVE
+ end
+ end
+ end
+ end
+ end # PMC
end
-
end
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