Kyösti Mälkki merged this change.
device/pci_ops: Drop unused parameter
Drop the bus parameter, we do not use it.
It would still be possible to do per-bus selection
by evaluating the bus number, but currently we do
not have need for that either.
Change-Id: I09e928b4677d9db2eee12730ba7b3fdd8837805c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
M src/arch/x86/pci_ops_conf1.c
M src/device/pci_ops.c
M src/device/pci_ops_mmconf.c
M src/include/device/pci.h
M src/southbridge/amd/rs780/rs780.c
M src/southbridge/amd/sr5650/pcie.c
6 files changed, 54 insertions(+), 65 deletions(-)
diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c
index e088463..1180a82 100644
--- a/src/arch/x86/pci_ops_conf1.c
+++ b/src/arch/x86/pci_ops_conf1.c
@@ -27,43 +27,40 @@
((where & 0xf00)<<16))
#endif
-static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn,
- int where)
+static uint8_t pci_conf1_read_config8(int bus, int devfn, int where)
{
outl(CONF_CMD(bus, devfn, where), 0xCF8);
return inb(0xCFC + (where & 3));
}
-static uint16_t pci_conf1_read_config16(struct bus *pbus, int bus, int devfn,
- int where)
+static uint16_t pci_conf1_read_config16(int bus, int devfn, int where)
{
outl(CONF_CMD(bus, devfn, where), 0xCF8);
return inw(0xCFC + (where & 2));
}
-static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn,
- int where)
+static uint32_t pci_conf1_read_config32(int bus, int devfn, int where)
{
outl(CONF_CMD(bus, devfn, where), 0xCF8);
return inl(0xCFC);
}
-static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn,
- int where, uint8_t value)
+static void pci_conf1_write_config8(int bus, int devfn, int where,
+ uint8_t value)
{
outl(CONF_CMD(bus, devfn, where), 0xCF8);
outb(value, 0xCFC + (where & 3));
}
-static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn,
- int where, uint16_t value)
+static void pci_conf1_write_config16(int bus, int devfn, int where,
+ uint16_t value)
{
outl(CONF_CMD(bus, devfn, where), 0xCF8);
outw(value, 0xCFC + (where & 2));
}
-static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn,
- int where, uint32_t value)
+static void pci_conf1_write_config32(int bus, int devfn, int where,
+ uint32_t value)
{
outl(CONF_CMD(bus, devfn, where), 0xCF8);
outl(value, 0xCFC);
diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c
index 82c22a7..de0bf63 100644
--- a/src/device/pci_ops.c
+++ b/src/device/pci_ops.c
@@ -70,41 +70,41 @@
u8 pci_read_config8(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
- return pci_bus_ops(pbus, dev)->read8(pbus, dev->bus->secondary,
+ return pci_bus_ops(pbus, dev)->read8(dev->bus->secondary,
dev->path.pci.devfn, where);
}
u16 pci_read_config16(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
- return pci_bus_ops(pbus, dev)->read16(pbus, dev->bus->secondary,
+ return pci_bus_ops(pbus, dev)->read16(dev->bus->secondary,
dev->path.pci.devfn, where);
}
u32 pci_read_config32(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
- return pci_bus_ops(pbus, dev)->read32(pbus, dev->bus->secondary,
+ return pci_bus_ops(pbus, dev)->read32(dev->bus->secondary,
dev->path.pci.devfn, where);
}
void pci_write_config8(struct device *dev, unsigned int where, u8 val)
{
struct bus *pbus = get_pbus(dev);
- pci_bus_ops(pbus, dev)->write8(pbus, dev->bus->secondary,
+ pci_bus_ops(pbus, dev)->write8(dev->bus->secondary,
dev->path.pci.devfn, where, val);
}
void pci_write_config16(struct device *dev, unsigned int where, u16 val)
{
struct bus *pbus = get_pbus(dev);
- pci_bus_ops(pbus, dev)->write16(pbus, dev->bus->secondary,
+ pci_bus_ops(pbus, dev)->write16(dev->bus->secondary,
dev->path.pci.devfn, where, val);
}
void pci_write_config32(struct device *dev, unsigned int where, u32 val)
{
struct bus *pbus = get_pbus(dev);
- pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary,
+ pci_bus_ops(pbus, dev)->write32(dev->bus->secondary,
dev->path.pci.devfn, where, val);
}
diff --git a/src/device/pci_ops_mmconf.c b/src/device/pci_ops_mmconf.c
index f321347..8b7b574 100644
--- a/src/device/pci_ops_mmconf.c
+++ b/src/device/pci_ops_mmconf.c
@@ -29,38 +29,35 @@
(((DEVFN) & 0xFF) << 12) |\
((WHERE) & 0xFFF)) & ~MASK))
-static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn,
- int where)
+static uint8_t pci_mmconf_read_config8(int bus, int devfn, int where)
{
return read8(PCI_MMIO_ADDR(bus, devfn, where, 0));
}
-static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn,
- int where)
+static uint16_t pci_mmconf_read_config16(int bus, int devfn, int where)
{
return read16(PCI_MMIO_ADDR(bus, devfn, where, 1));
}
-static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn,
- int where)
+static uint32_t pci_mmconf_read_config32(int bus, int devfn, int where)
{
return read32(PCI_MMIO_ADDR(bus, devfn, where, 3));
}
-static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn,
- int where, uint8_t value)
+static void pci_mmconf_write_config8(int bus, int devfn, int where,
+ uint8_t value)
{
write8(PCI_MMIO_ADDR(bus, devfn, where, 0), value);
}
-static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn,
- int where, uint16_t value)
+static void pci_mmconf_write_config16(int bus, int devfn, int where,
+ uint16_t value)
{
write16(PCI_MMIO_ADDR(bus, devfn, where, 1), value);
}
-static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn,
- int where, uint32_t value)
+static void pci_mmconf_write_config32(int bus, int devfn, int where,
+ uint32_t value)
{
write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value);
}
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 814433d..0ead578 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -36,15 +36,12 @@
/* Common pci bus operations */
struct pci_bus_operations {
- uint8_t (*read8)(struct bus *pbus, int bus, int devfn, int where);
- uint16_t (*read16)(struct bus *pbus, int bus, int devfn, int where);
- uint32_t (*read32)(struct bus *pbus, int bus, int devfn, int where);
- void (*write8)(struct bus *pbus, int bus, int devfn, int where,
- uint8_t val);
- void (*write16)(struct bus *pbus, int bus, int devfn, int where,
- uint16_t val);
- void (*write32)(struct bus *pbus, int bus, int devfn, int where,
- uint32_t val);
+ uint8_t (*read8)(int bus, int devfn, int where);
+ uint16_t (*read16)(int bus, int devfn, int where);
+ uint32_t (*read32)(int bus, int devfn, int where);
+ void (*write8)(int bus, int devfn, int where, uint8_t val);
+ void (*write16)(int bus, int devfn, int where, uint16_t val);
+ void (*write32)(int bus, int devfn, int where, uint32_t val);
};
struct pci_driver {
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index c5e38c1..28e337f 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -31,33 +31,32 @@
u32 reg;
u16 word;
u8 byte;
- struct bus pbus; /* fake bus for dev0 fun1 */
reg = pci_read_config32(nb_dev, 0x4c);
reg |= 1 << 0;
pci_write_config32(nb_dev, 0x4c, reg);
- word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
+ word = pci_cf8_conf1.read16(0, 1, 0xf8);
word &= 0xf00;
- pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
+ pci_cf8_conf1.write16(0, 1, 0xf8, word);
- word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
+ word = pci_cf8_conf1.read16(0, 1, 0xe8);
word &= ~((1 << 12) | (1 << 13) | (1 << 14));
word |= 1 << 13;
- pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word);
+ pci_cf8_conf1.write16(0, 1, 0xe8, word);
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+ reg = pci_cf8_conf1.read32(0, 1, 0x94);
reg &= ~((1 << 16) | (1 << 24) | (1 << 28));
- pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+ pci_cf8_conf1.write32(0, 1, 0x94, reg);
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
+ reg = pci_cf8_conf1.read32(0, 1, 0x8c);
reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25));
reg |= 1 << 13;
- pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
+ pci_cf8_conf1.write32(0, 1, 0x8c, reg);
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+ reg = pci_cf8_conf1.read32(0, 1, 0xcc);
reg |= 1 << 24;
- pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+ pci_cf8_conf1.write32(0, 1, 0xcc, reg);
reg = nbmc_read_index(nb_dev, 0x7a);
reg &= ~0x3f;
@@ -66,31 +65,31 @@
set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
nbmc_write_index(nb_dev, 0x7a, reg);
/* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+ reg = pci_cf8_conf1.read32(0, 1, 0xcc);
reg &= ~(1 << 23);
reg |= 1 << 24;
- pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+ pci_cf8_conf1.write32(0, 1, 0xcc, reg);
/* Programming NB CLK table. */
- byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe0);
+ byte = pci_cf8_conf1.read8(0, 1, 0xe0);
byte |= 0x01;
- pci_cf8_conf1.write8(&pbus, 0, 1, 0xe0, byte);
+ pci_cf8_conf1.write8(0, 1, 0xe0, byte);
#if 0
/* Powerdown reference clock to graphics core PLL in northbridge only mode */
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
+ reg = pci_cf8_conf1.read32(0, 1, 0x8c);
reg |= 1 << 21;
- pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
+ pci_cf8_conf1.write32(0, 1, 0x8c, reg);
/* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
+ reg = pci_cf8_conf1.read32(0, 1, 0xcc);
reg |= (1 << 23) | (1 << 24);
- pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
+ pci_cf8_conf1.write32(0, 1, 0xcc, reg);
/* Powerdown clock to memory controller in northbridge only mode */
- byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4);
+ byte = pci_cf8_conf1.read8(0, 1, 0xe4);
byte |= 1 << 0;
- pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg);
+ pci_cf8_conf1.write8(0, 1, 0xe4, reg);
/* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */
/* TODO: */
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index 9d4c689..763dd01 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -888,7 +888,6 @@
void pcie_config_misc_clk(struct device *nb_dev)
{
u32 reg;
- //struct bus pbus; /* fake bus for dev0 fun1 */
reg = pci_read_config32(nb_dev, 0x4c);
reg |= 1 << 0;
@@ -902,9 +901,9 @@
set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
/* LCLK Clock Gating */
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+ reg = pci_cf8_conf1.read32(0, 1, 0x94);
reg &= ~(1 << 16);
- pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+ pci_cf8_conf1.write32(0, 1, 0x94, reg);
}
if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
@@ -914,9 +913,9 @@
set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_SB, (3 << 6) | (~0xf), 3 << 6);
/* LCLK Clock Gating */
- reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
+ reg = pci_cf8_conf1.read32(0, 1, 0x94);
reg &= ~(1 << 24);
- pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
+ pci_cf8_conf1.write32(0, 1, 0x94, reg);
}
#endif
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