Michał Żygowski has uploaded this change for review.
cpu/amd/family_10h-family_15h: Remove fidvid.c include
Do bare minimum to remove the C source include. The migrated functions
maybe are not in the right places for now, but will be regrouped in
further patches.
TEST=build tested KGPE-D16
Change-Id: I74b2784b27e7e8664ebf842173d57841602bef3e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
---
M src/cpu/amd/family_10h-family_15h/Makefile.inc
M src/cpu/amd/family_10h-family_15h/fidvid.c
A src/cpu/amd/family_10h-family_15h/fidvid.h
M src/cpu/amd/family_10h-family_15h/init_cpus.c
M src/cpu/amd/family_10h-family_15h/init_cpus.h
M src/cpu/amd/quadcore/quadcore.c
M src/include/cpu/amd/multicore.h
7 files changed, 57 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/48463/1
diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
index 7035323..f116042 100644
--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
@@ -2,6 +2,7 @@
romstage-y += ../car/post_cache_as_ram.c
romstage-y += init_cpus.c
+romstage-y += fidvid.c
ramstage-y += model_10xxx_init.c
ramstage-y += processor_name.c
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
index 57207a4..a2140a1 100644
--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
@@ -88,9 +88,13 @@
#include <console/console.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/multicore.h>
#include <device/pci_ops.h>
#include <stdint.h>
#include <northbridge/amd/amdht/AsPsDefs.h>
+#include <northbridge/amd/amdht/ht_wrapper.h>
+#include <cpu/amd/family_10h-family_15h/init_cpus.h>
+#include <cpu/amd/family_10h-family_15h/fidvid.h>
#include <stdlib.h>
static inline void print_debug_fv(const char *str, u32 val)
@@ -861,7 +865,7 @@
}
-static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid)
+void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid)
{
u32 send;
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.h b/src/cpu/amd/family_10h-family_15h/fidvid.h
new file mode 100644
index 0000000..fe092fb
--- /dev/null
+++ b/src/cpu/amd/family_10h-family_15h/fidvid.h
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
\ No newline at end of file
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
index 452f7ce..61598d2 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -27,7 +27,7 @@
#include <northbridge/amd/amdht/AsPsDefs.h>
#include <northbridge/amd/amdht/porting.h>
#include <northbridge/amd/amdht/h3ncmn.h>
-
+#include <cpu/amd/family_10h-family_15h/fidvid.h>
#include <southbridge/amd/common/reset.h>
#if CONFIG(SOUTHBRIDGE_AMD_SB700)
@@ -142,7 +142,7 @@
//core range = 1 : core 0 only
//core range = 2 : cores other than core0
-static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
+void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
process_ap_t process_ap, void *gp)
{
// here assume the OS don't change our apicid
@@ -202,7 +202,7 @@
}
}
-static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
+int lapic_remote_read(int apicid, int reg, u32 *pvalue)
{
int timeout;
u32 status;
@@ -231,10 +231,6 @@
return result;
}
-#if CONFIG(SET_FIDVID)
-static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
-#endif
-
static __always_inline
void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id,
const char *str)
@@ -774,32 +770,6 @@
}
}
-static u32 get_platform_type(void)
-{
- u32 ret = 0;
-
- switch (SYSTEM_TYPE) {
- case 1:
- ret |= AMD_PTYPE_DSK;
- break;
- case 2:
- ret |= AMD_PTYPE_MOB;
- break;
- case 0:
- ret |= AMD_PTYPE_SVR;
- break;
- default:
- break;
- }
-
- /* FIXME: add UMA support. */
-
- /* All Fam10 are multi core */
- ret |= AMD_PTYPE_MC;
-
- return ret;
-}
-
static void AMD_SetupPSIVID_d(u32 platform_type, u8 node)
{
u32 dword;
@@ -835,7 +805,7 @@
*
* Returns the offset of the link register.
*/
-static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset)
+BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset)
{
u32 reg;
u32 val;
@@ -875,7 +845,7 @@
*
* Returns the link characteristic mask.
*/
-static u32 AMD_checkLinkType(u8 node, u8 regoff)
+u32 AMD_checkLinkType(u8 node, u8 regoff)
{
uint32_t val;
uint32_t val2;
@@ -1882,7 +1852,3 @@
}
#endif
}
-
-#if CONFIG(SET_FIDVID)
-# include "fidvid.c"
-#endif
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h
index 4be6ee8..5fb6134 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.h
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h
@@ -39,6 +39,11 @@
uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2);
void start_other_cores(uint32_t bsp_apicid);
u32 get_core_num_in_bsp(u32 nodeid);
+int lapic_remote_read(int apicid, int reg, u32 *pvalue);
+BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset);
+u32 AMD_checkLinkType(u8 node, u8 regoff);
+void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
+ process_ap_t process_ap, void *gp);
void update_microcode(u32 cpu_deviceid);
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index 454462f..3311d8d 100644
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -23,6 +23,32 @@
#include "option_table.h"
#endif
+u32 get_platform_type(void)
+{
+ u32 ret = 0;
+
+ switch (SYSTEM_TYPE) {
+ case 1:
+ ret |= AMD_PTYPE_DSK;
+ break;
+ case 2:
+ ret |= AMD_PTYPE_MOB;
+ break;
+ case 0:
+ ret |= AMD_PTYPE_SVR;
+ break;
+ default:
+ break;
+ }
+
+ /* FIXME: add UMA support. */
+
+ /* All Fam10 are multi core */
+ ret |= AMD_PTYPE_MC;
+
+ return ret;
+}
+
u32 get_core_num_in_bsp(u32 nodeid)
{
u32 dword;
diff --git a/src/include/cpu/amd/multicore.h b/src/include/cpu/amd/multicore.h
index 79bea66..c7b28a6 100644
--- a/src/include/cpu/amd/multicore.h
+++ b/src/include/cpu/amd/multicore.h
@@ -39,5 +39,6 @@
void wait_all_other_cores_stopped(uint32_t bsp_apicid);
void allow_all_aps_stop(u32 bsp_apicid);
u32 get_initial_apicid(void);
+u32 get_platform_type(void);
#endif /* CPU_AMD_QUADCORE_H */
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