David Wu uploaded patch set #4 to this change.

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soc/intel/cannonlake: Clear the GPI IS & IE registers

Clear the GPI Interrupt Status & Enable registers to prevent any
interrupt storms due to GPI.

BUG=b:138282962
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot-up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.

Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
---
M src/soc/intel/cannonlake/chip.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/34624/4

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