Patch set 1:Code-Review -1
2 comments:
Patch Set #1, Line 10: alignment requirments.
What is the further motivation here? Reducing variable MTRR usage? The algorithms take into account natural alignment. However, if the memory map is not aligned well then cbmem_top() should be the entity providing the alignment.
File src/soc/intel/cannonlake/romstage/romstage.c:
Patch Set #1, Line 162: top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size);
> It does what the comment says, at least 8 MiB below, at most 8 MiB above cbmem_top() will be WB. […]
I really don't see what this change provides. It doesn't guarantee the memory we're actually using is covered. It's optimizing for MTRR usage while not guaranteeing the region we're using is covered.
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