Lijian Zhao uploaded patch set #2 to this change.

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soc/intel/cannonlake: Enable ISH from device

PCH ISH enabled/disabled in FSP memory init UPD, it will be match the
setting in ISH device on/off in devicetree.cb.

BUG=N/A
TEST=Build and pass on whiskey lake rvp platform.

Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
---
M src/soc/intel/cannonlake/romstage/fsp_params.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29274/2

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68
Gerrit-Change-Number: 29274
Gerrit-PatchSet: 2
Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com>
Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula@intel.com>
Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim@intel.com>
Gerrit-Reviewer: Li1 Feng <li1.feng@intel.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com>
Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>