V Sowmya has uploaded this change for review.

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soc/intel/cannonlake: Add an option to enable or disable IPU

This patch provides an option to enable or disable IPU (image processing unit),
* Expose SaIpuEnable FSP UPD param in chip.h.
* Add an entry for SA IPU in the pci_devs.h.
* Enable/Disable the IPU based on device status.

Change-Id: Ia155bc242dd33e816d056bbea1e3d4c1cbbe23da
Signed-off-by: V Sowmya <v.sowmya@intel.com>
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/include/soc/pci_devs.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
3 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30698/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 3a723d2..5ef516c 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -110,6 +110,8 @@
SaGv_Enabled,
} SaGv;

+ /* SA IPU (Image Processing Unit) */
+ uint8_t SaIpuEnabled;

/* Rank Margin Tool. 1:Enable, 0:Disable */
uint8_t RMT;
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index 77ae746..005cda3 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -47,6 +47,10 @@
#define SA_DEVFN_DSP _SA_DEVFN(DSP)
#define SA_DEV_DSP _SA_DEV(DSP)

+#define SA_DEV_SLOT_IPU 0x05
+#define SA_DEVFN_IPU _SA_DEVFN(IPU)
+#define SA_DEV_IPU _SA_DEV(IPU)
+
/* PCH Devices */
#define PCH_DEV_SLOT_THERMAL 0x12
#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0)
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index c3a2509..ab1bfc0 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -67,6 +67,12 @@
else
m_cfg->PchHdaEnable = dev->enabled;

+ /* Enable IPU only if the device is enabled */
+ dev = dev_find_slot(0, SA_DEVFN_IPU);
+ if (!dev)
+ m_cfg->SaIpuEnable = 0;
+ else
+ m_cfg->SaIpuEnable = dev->enabled;
}

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia155bc242dd33e816d056bbea1e3d4c1cbbe23da
Gerrit-Change-Number: 30698
Gerrit-PatchSet: 1
Gerrit-Owner: V Sowmya <v.sowmya@intel.com>
Gerrit-MessageType: newchange