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Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84906?usp=email
to look at the new patch set (#8).
Change subject: soc/amd/common/psp_smi_flash: implement SPI flash RPMC command handling ......................................................................
soc/amd/common/psp_smi_flash: implement SPI flash RPMC command handling
Extend the 'psp_smi_spi_rpmc_inc_mc' and 'psp_smi_spi_rpmc_req_mc' function stubs than now implement the actual functionality by calling 'spi_flash_rpmc_increment' and 'spi_flash_rpmc_request' after doing some sanity checks.
TEST=When selecting both 'SOC_AMD_COMMON_BLOCK_PSP_RPMC' and 'SOC_AMD_COMMON_BLOCK_PSP_SMI' Kconfig options on a board with an RPMC- capable SPI flash, the PSP SMI handler can successfully service not only the already working SPI flash write command, but also the increment monotonic counter RPMC command:
[NOTE ] coreboot-[...] x86_32 smm starting (log level: 8)...
[SPEW ] SMI# #0 [SPEW ] PSP: SPI write request [DEBUG] FMAP: area PSP_NVRAM found @ f20000 (131072 bytes) [SPEW ] PSP: SPI write 0x400 bytes at 0x0
[NOTE ] coreboot-[...] x86_32 smm starting (log level: 8)...
[SPEW ] SMI# #0 [SPEW ] PSP: SPI write request [DEBUG] FMAP: area PSP_NVRAM found @ f20000 (131072 bytes) [SPEW ] PSP: SPI write 0x400 bytes at 0x400
[NOTE ] coreboot-[...] x86_32 smm starting (log level: 8)...
[SPEW ] SMI# #8 [SPEW ] PSP: SPI write request [DEBUG] FMAP: area PSP_NVRAM found @ f20000 (131072 bytes) [SPEW ] PSP: SPI write 0x310 bytes at 0x800
[NOTE ] coreboot-[...] x86_32 smm starting (log level: 8)...
[SPEW ] SMI# #1 [SPEW ] PSP: SPI write request [DEBUG] FMAP: area PSP_RPMC_NVRAM found @ f40000 (262144 bytes) [SPEW ] PSP: SPI write 0x70 bytes at 0x100
[NOTE ] coreboot-[...] x86_32 smm starting (log level: 8)...
[SPEW ] SMI# #0 [SPEW ] PSP: SPI RPMC increment monotonic counter request
This requires the PSP_RPMC_NVRAM FMAP section to have the correct size which in case of Renoir is 256 kByte. Having this large enough size also makes the PSP report that the PSP RPMC NVRAM is healthy which wasn't the case in previous tests when the region was too small.
Change-Id: I20e4f60d4e35d33e560fc43212b320e817e13004 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/psp_smi_flash.c 2 files changed, 41 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/84906/8