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1 comment:

• File src/soc/intel/common/block/cpu/cpulib.c:

  • Patch Set #2, Line 277:

    /* Time Window Tau Bits [6:0] */
    	msr.lo &= ~0x7f;
    	msr.lo |= 0xe6; /* setting 100ms thermal time window */
    	wrmsr(MSR_TEMPERATURE_TARGET, msr);
    

    If I have a look at the MSR documentation of Apollo Lake then I will find that bits 0.. […]

    That's fair. It looks like from cannonlake onwards, those bits are as expected here (time window bits). I'll supplement this with a guard to exclude APL and before, since from the EDSs I have, all SoC's after that appear to have the bits defined that way.

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