Lijian Zhao has uploaded this change for review.

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soc/intel/cannonlake: Add option for boot frquency

Cannonlake/Coffeelake FSP have options for CPU boot up frequency
selection, expose that in coreboot side.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30445/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 3a723d2..7e50a73 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -110,6 +110,11 @@
 		SaGv_Enabled,
 	} SaGv;
 
+	/* Boot Frequency from reset vector.
+	 * 0: Maximum battery performance, 1: Maximum non-turbo performance, 2:
+	 * Maximum turbo performance @note If 2 is selected, system will start
+	 * with non-turbo mode and then switch to turbo. */
+	uint8_t bootfreq;
 
 	/* Rank Margin Tool. 1:Enable, 0:Disable */
 	uint8_t RMT;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index c3a2509..0514844 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -54,6 +54,8 @@
 #if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
 	m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
 #endif
+	m_cfg->BootFrequency = config->bootfreq;
+
 	/* If ISH is enabled, enable ISH elements */
 	if (!dev)
 		m_cfg->PchIshEnable = 0;

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