Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60774 )
Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support ......................................................................
soc/intel/common/gpio: Rework PAD config macro to add lock support
This patch creates new GPIO PAD configuration macros that would help toperform GPIO pad configuration and pad lock configuration as well.
Lists of new macros are: 1. PAD_CFG_NF_LOCK 2. PAD_CFG_GPO_LOCK 3. PAD_CFG_GPI_LOCK 4. PAD_CFG_GPI_TRIG_OWN_LOCK 5. PAD_CFG_GPI_GPIO_DRIVER_LOCK 6. PAD_CFG_GPI_INT_LOCK 7. PAD_CFG_GPI_APIC_LOCK 8. PAD_CFG_GPI_IRQ_WAKE_LOCK
Mainboard users can use the above macros to lock the PAD after configuration.
So far on IA chipset. the default GPIO pad lock configuration reset type is POWERGOOD hence, its recommended as per GPIO BWG (doc: 630603) to configure the GPP PAD reset type as same as lock configuration reset type to avoid GPP reset value misconfiguration issue.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 3 files changed, 79 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/60774/1
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 419c77e..3a6f7b7 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -341,6 +341,8 @@ gpio_configure_owner(cfg, comm); gpi_enable_smi(cfg, comm); gpi_enable_nmi(cfg, comm); + if (cfg->action) + gpio_lock_pad(cfg->pad, cfg->action); }
void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 700b975..5342f76 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -65,10 +65,18 @@
typedef uint32_t gpio_t;
+enum gpio_lock_action { + GPIO_UNLOCK = 0x0, + GPIO_LOCK_CONFIG = 0x1, + GPIO_LOCK_TX = 0x2, + GPIO_LOCK_FULL = GPIO_LOCK_CONFIG | GPIO_LOCK_TX, +}; + struct pad_config { gpio_t pad;/* offset of pad within community */ uint32_t pad_config[GPIO_NUM_PAD_CFG_REGS];/* Pad config data corresponding to DW0, DW1,.... */ + enum gpio_lock_action action; /* Pad lock configuration */ };
/* @@ -199,12 +207,6 @@ */ void *gpio_dwx_address(const gpio_t pad);
-enum gpio_lock_action { - GPIO_LOCK_CONFIG = 0x1, - GPIO_LOCK_TX = 0x2, - GPIO_LOCK_FULL = GPIO_LOCK_CONFIG | GPIO_LOCK_TX, -}; - struct gpio_lock_config { gpio_t pad; enum gpio_lock_action action; diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index d3249bc..53b2f0e 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -129,6 +129,7 @@ #define PAD_IRQ_ROUTE(value) PAD_CFG0_ROUTE_##value #define PAD_TRIG(value) PAD_CFG0_TRIG_##value #define PAD_PULL(value) PAD_CFG1_PULL_##value +#define PAD_LOCK(value) GPIO_##value
/* Disable the input/output buffer of the pad */ #define PAD_CFG0_BUF_NO_DISABLE (0) @@ -165,6 +166,15 @@ .pad = __pad, \ .pad_config[0] = __config0, \ .pad_config[1] = __config1, \ + .action = PAD_LOCK(UNLOCK), \ + } + +#define _PAD_CFG_STRUCT_LOCK(__pad, __config0, __config1, __action) \ + { \ + .pad = __pad, \ + .pad_config[0] = __config0, \ + .pad_config[1] = __config1, \ + .action = __action, \ }
#if GPIO_NUM_PAD_CFG_REGS > 2 @@ -174,6 +184,7 @@ .pad_config[0] = __config0, \ .pad_config[1] = __config1, \ .pad_config[2] = __config2, \ + .action = PAD_LOCK(UNLOCK), \ } #else #define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \ @@ -186,6 +197,13 @@ PAD_RESET(rst) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
+/* Native function configuration with lock */ +#define PAD_CFG_NF_LOCK(pad, pull, func, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_RESET(PWROK) | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE), \ + PAD_LOCK(action)) + #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S Not applicable to all SOCs. Refer EDS @@ -230,6 +248,14 @@ PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
+/* General purpose output with lock, no pullup/down. */ +#define PAD_CFG_GPO_LOCK(pad, val, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE), \ + PAD_LOCK(action)) + /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ @@ -258,6 +284,13 @@ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
+/* General purpose input with lock */ +#define PAD_CFG_GPI_LOCK(pad, pull, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \ + PAD_LOCK(action)) + #define PAD_CFG_GPI_TRIG_IOSSTATE_OWN(pad, pull, rst, trig, iosstate, own) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | PAD_BUF(TX_DISABLE), \ @@ -279,12 +312,26 @@ PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
+#define PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, rst, trig, own, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), \ + PAD_LOCK(action)) + #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE))
+#define PAD_CFG_GPI_GPIO_DRIVER_LOCK(pad, pull, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | \ + PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE), \ + PAD_LOCK(action)) + #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ @@ -300,6 +347,10 @@ #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER)
+/* GPIO Interrupt with lock */ +#define PAD_CFG_GPI_INT_LOCK(pad, pull, trig, action) \ + PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, PWROK, trig, DRIVER, action) + /* * No Connect configuration for unconnected or unused pad. * Both TX and RX are disabled. RX disabling is done to avoid unnecessary @@ -319,6 +370,14 @@ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE))
+/* General purpose input with lock, routed to APIC */ +#define PAD_CFG_GPI_APIC_LOCK(pad, pull, trig, inv, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxDRxE), \ + PAD_LOCK(action)) + /* General purpose input, routed to APIC - with IOStandby Config*/ #define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ @@ -406,9 +465,19 @@ PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
+#define PAD_CFG_GPI_DUAL_ROUTE_LOCK(pad, pull, rst, trig, inv, route1, route2, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \ + PAD_LOCK(action)) + #define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI)
+#define PAD_CFG_GPI_IRQ_WAKE_LOCK(pad, pull, trig, inv, action) \ + PAD_CFG_GPI_DUAL_ROUTE_LOCK(pad, pull, PWROK, trig, inv, IOAPIC, SCI, action) + #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */
#endif /* _SOC_BLOCK_GPIO_DEFS_H_ */