[coreboot-gerrit] [XS] Change in coreboot[master]: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config

[Subrata Banik (Code Review)]

Attention is currently required from: Andrey Petrov, Arthur Heymans, Christian Walter, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Nill Ge, Reka Norman, Shuo Liu, TangYiwei, Tim Chu.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email )

Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
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Patch Set 2:

(1 comment)

Patchset:

PS1:
> > > The problem of seeing "SPI Transaction Timeout" at BS_DEV_RESOURCES is not related to your cls, but with your cls because it's moved to a later stage after BS_DEV_RESOURCES, then it cannot write MRC data.
> > >
> > > I still resolve this comment, just providing some test results for thoughts.
> >
> > @Johnny, can you please help me to debug this issue on AC by commenting below code and share if u r still seeing the timeout issue. I'm suspecting the SPI is getting locked is the reason for this problem
> > BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,
> >    			NULL);
> >
> > BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, lock, NULL);
>
> As per my understanding the issue is coming because of applying the BIOS Decode lock so early in the boot
> void spi_lockdown_config(int chipset_lockdown)
> {
>    if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
>    	fast_spi_set_bde();
>    	fast_spi_set_vcl();
>    }
> }
>
> can you please check by commenting on this function ? alternatively we shall call BDE and VCL from soc_finalize() ?

@Jonny, can you please pick the updated patch train and share your feedback?