Shreesh Chhabbi would like John Zhao and Shreesh Chhabbi to review this change.

View Change

Enable TCSS devices PM based on platform device tree setting

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I3044d5f4a882849abd87e313e65189659d503bfb
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
---
M src/soc/intel/tigerlake/acpi/tcss.asl
1 file changed, 58 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/42771/1

diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
index 48f2689..24ca891 100644
--- a/src/soc/intel/tigerlake/acpi/tcss.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -252,6 +252,25 @@
 Scope (\_SB.PCI0)
 {
 	/*
+	 * Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset
+	 * 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR.
+	 */
+	OperationRegion (TDEN, SystemMemory, (GMHB() + 0x7090), 0x4)
+	Field (TDEN, ByteAcc, NoLock, Preserve)
+	{
+		TRE0, 1,  /* PCIE0_EN */
+		TRE1, 1,  /* PCIE1_EN */
+		TRE2, 1,  /* PCIE2_EN */
+		TRE3, 1,  /* PCIE3_EN */
+		,     4,
+		THCE, 1,  /* XHCI_EN */
+		TDCE, 1,  /* XDCI_EN */
+		DME0, 1,  /* TBT_DMA0_EN */
+		DME1, 1,  /* TBT_DMA1_EN */
+		,     20
+	}
+
+	/*
 	 * Operation region defined to access the IOM REGBAR. Get the MCHBAR in offset
 	 * 0x48 in B0:D0:F0. REGBAR Base address is in offset 0x7110 of MCHBAR.
 	 */
@@ -763,7 +782,11 @@
 
 		Method (_STA, 0x0, NotSerialized)
 		{
-			Return (0x0F)
+			If (THCE == 1) {
+				Return (0x0F)
+			} Else {
+				Return (0x0)
+			}
 		}
 		#include "tcss_xhci.asl"
 	}
@@ -781,7 +804,11 @@
 
 		Method (_STA, 0x0, NotSerialized)
 		{
-			Return (0x0F)
+			If (DME0 == 1) {
+				Return (0x0F)
+			} Else {
+				Return (0x0)
+			}
 		}
 		#include "tcss_dma.asl"
 	}
@@ -799,7 +826,11 @@
 
 		Method (_STA, 0x0, NotSerialized)
 		{
-			Return (0x0F)
+			If (DME1 == 1) {
+				Return (0x0F)
+			} Else {
+				Return (0x0)
+			}
 		}
 		#include "tcss_dma.asl"
 	}
@@ -818,8 +849,13 @@
 
 		Method (_STA, 0x0, NotSerialized)
 		{
-			Return (0x0F)
+			If (TRE0 == 1) {
+				Return (0x0F)
+			} Else {
+				Return (0x0)
+			}
 		}
+
 		Method (_INI)
 		{
 			LTEN = 0
@@ -843,8 +879,13 @@
 
 		Method (_STA, 0x0, NotSerialized)
 		{
-			Return (0x0F)
+			If (TRE1 == 1) {
+				Return (0x0F)
+			} Else {
+				Return (0x0)
+			}
 		}
+
 		Method (_INI)
 		{
 			LTEN = 0
@@ -868,8 +909,13 @@
 
 		Method (_STA, 0x0, NotSerialized)
 		{
-			Return (0x0F)
+			If (TRE2 == 1) {
+				Return (0x0F)
+			} Else {
+				Return (0x0)
+			}
 		}
+
 		Method (_INI)
 		{
 			LTEN = 0
@@ -893,8 +939,13 @@
 
 		Method (_STA, 0x0, NotSerialized)
 		{
-			Return (0x0F)
+			If (TRE3 == 1) {
+				Return (0x0F)
+			} Else {
+				Return (0x0)
+			}
 		}
+
 		Method (_INI)
 		{
 			LTEN = 0

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