[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/{common, meteorlake}: Add support for new MCH

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72835 )

Change subject: soc/intel/{common, meteorlake}: Add support for new MCH
......................................................................

soc/intel/{common, meteorlake}: Add support for new MCH

The patch adds support for new Meteor Lake MCH (ID:0x7d16).

TEST=Build and boot the system having MCH ID:0x7d16.

Signed-off-by: Sridhar Siricilla 
Change-Id: Ib0c9ce5c58e4bdec5e7245840f0892d651922cd9
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/meteorlake/bootblock/report_platform.c
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/systemagent.c
5 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/72835/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index dbc1706..6c32620 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4106,6 +4106,7 @@
 #define PCI_DID_INTEL_MTL_P_ID_2		0x7D02
 #define PCI_DID_INTEL_MTL_P_ID_3		0x7d14
 #define PCI_DID_INTEL_MTL_P_ID_4		0x7d15
+#define PCI_DID_INTEL_MTL_P_ID_5		0x7d16
 #define PCI_DID_INTEL_RPL_P_ID_1		0xa706
 #define PCI_DID_INTEL_RPL_P_ID_2		0xa707
 #define PCI_DID_INTEL_RPL_P_ID_3		0xa708
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index aeeff12..174d511 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -341,6 +341,7 @@
    PCI_DID_INTEL_MTL_P_ID_2,
    PCI_DID_INTEL_MTL_P_ID_3,
    PCI_DID_INTEL_MTL_P_ID_4,
+	PCI_DID_INTEL_MTL_P_ID_5,
    PCI_DID_INTEL_GLK_NB,
    PCI_DID_INTEL_APL_NB,
    PCI_DID_INTEL_CNL_ID_U,
diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c
index 982a0c5..a5d32f3 100644
--- a/src/soc/intel/meteorlake/bootblock/report_platform.c
+++ b/src/soc/intel/meteorlake/bootblock/report_platform.c
@@ -30,6 +30,7 @@
    { PCI_DID_INTEL_MTL_P_ID_2, "MeteorLake P" },
    { PCI_DID_INTEL_MTL_P_ID_3, "MeteorLake P" },
    { PCI_DID_INTEL_MTL_P_ID_4, "MeteorLake P" },
+	{ PCI_DID_INTEL_MTL_P_ID_5, "MeteorLake P" },
 };

static struct {
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index 4e95321..9403980 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -23,6 +23,7 @@
    MTL_P_POWER_LIMITS_2,
    MTL_P_POWER_LIMITS_3,
    MTL_P_POWER_LIMITS_4,
+	MTL_P_POWER_LIMITS_5,
    MTL_POWER_LIMITS_COUNT
 };

diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c
index 81e4bed..c133966 100644
--- a/src/soc/intel/meteorlake/systemagent.c
+++ b/src/soc/intel/meteorlake/systemagent.c
@@ -181,6 +181,9 @@
    case PCI_DID_INTEL_MTL_P_ID_4:
    	soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_4];
    	break;
+	case PCI_DID_INTEL_MTL_P_ID_5:
+		soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_5];
+		break;
    default:
    	printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipping power limits configuration\n",
    		sa_pci_id);