Patrick Georgi submitted this change.
mediatek/mt8183: Allow modifying vcore voltage
Because vcore is the power of ddrphy in the soc, DRAM DVFS needs to be
calibrated with different vcore voltages to get correct parameters.
A new API is added to allow changing vcore voltage.
BUG=b:80501386
BRANCH=none
TEST=measure vcore voltage with multimeter
Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33391
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/soc/mediatek/mt8183/include/soc/mt6358.h
M src/soc/mediatek/mt8183/mt6358.c
2 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h
index 19ab5e1..bb5f019 100644
--- a/src/soc/mediatek/mt8183/include/soc/mt6358.h
+++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h
@@ -25,6 +25,9 @@
PMIC_TOP_TMA_KEY = 0x03a8,
PMIC_PWRHOLD = 0x0a08,
PMIC_CPSDSA4 = 0x0a2e,
+ PMIC_VCORE_OP_EN = 0x1490,
+ PMIC_VCORE_DBG0 = 0x149e,
+ PMIC_VCORE_VOSEL = 0x14aa,
PMIC_VDRAM1_VOSEL_SLEEP = 0x160a,
PMIC_SMPS_ANA_CON0 = 0x1808,
PMIC_VSIM2_ANA_CON0 = 0x1e30,
@@ -41,5 +44,7 @@
void pmic_set_power_hold(bool enable);
void pmic_set_vsim2_cali(unsigned int vsim2_mv);
void pmic_init_scp_voltage(void);
+unsigned int pmic_get_vcore_vol(void);
+void pmic_set_vcore_vol(unsigned int vcore_uv);
#endif /* __SOC_MEDIATEK_MT6358_H__ */
diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c
index fa928cb..3600b6a 100644
--- a/src/soc/mediatek/mt8183/mt6358.c
+++ b/src/soc/mediatek/mt8183/mt6358.c
@@ -805,6 +805,27 @@
pwrap_write_field(PMIC_VSIM2_ANA_CON0, cali_mv / 10, 0xF, 0);
}
+unsigned int pmic_get_vcore_vol(void)
+{
+ unsigned int vol_reg;
+
+ vol_reg = pwrap_read_field(PMIC_VCORE_DBG0, 0x7F, 0);
+ return 500000 + vol_reg * 6250;
+}
+
+void pmic_set_vcore_vol(unsigned int vcore_uv)
+{
+ unsigned int vol_reg;
+
+ assert(vcore_uv >= 500000);
+ assert(vcore_uv <= 1100000);
+
+ vol_reg = (vcore_uv - 500000) / 6250;
+
+ pwrap_write_field(PMIC_VCORE_OP_EN, 1, 0x7F, 0);
+ pwrap_write_field(PMIC_VCORE_VOSEL, vol_reg, 0x7F, 0);
+}
+
static void pmic_wdt_set(void)
{
/* [5]=1, RG_WDTRSTB_DEB */
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