Subrata Banik submitted this change.
mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllers
This patch enables TCSS xDCI, TBT PCIe root ports and DMA controllers
for ADLRVP.
BUG=b:170607415
TEST=Built and booted on ADLRVP.
Change-Id: Iabd6cc7c589d1c20cde9d66c0a63e2cf16316b33
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47288
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
index ea75d5d..44c324b 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
@@ -173,17 +173,17 @@
device pci 04.0 on end # DPTF
device pci 05.0 on end # IPU
device pci 06.0 on end # PEG60
- device pci 07.0 off end # TBT_PCIe0
- device pci 07.1 off end # TBT_PCIe1
- device pci 07.2 off end # TBT_PCIe2
- device pci 07.3 off end # TBT_PCIe3
+ device pci 07.0 on end # TBT_PCIe0
+ device pci 07.1 on end # TBT_PCIe1
+ device pci 07.2 on end # TBT_PCIe2
+ device pci 07.3 on end # TBT_PCIe3
device pci 08.0 off end # GNA
device pci 09.0 off end # NPK
device pci 0a.0 off end # Crash-log SRAM
device pci 0d.0 on end # USB xHCI
- device pci 0d.1 off end # USB xDCI (OTG)
- device pci 0d.2 off end # TBT DMA0
- device pci 0d.3 off end # TBT DMA1
+ device pci 0d.1 on end # USB xDCI (OTG)
+ device pci 0d.2 on end # TBT DMA0
+ device pci 0d.3 on end # TBT DMA1
device pci 0e.0 off end # VMD
device pci 10.0 off end
device pci 10.1 off end
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