All the actual Volteer variants will have CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) enabled, and in that case, it is obvious to see that this CL is a no-op.

Only the reworked Volteer prototypes, hooked up with external Dauntless development board, will use I2C instead of SPI for TPM communication, and could be affected by the logic change here.

Furquan, could you please +2 this.

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce
Gerrit-Change-Number: 47049
Gerrit-PatchSet: 7
Gerrit-Owner: Jes Klinke <jbk@chromium.org>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Jes Klinke <jbk@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-Comment-Date: Wed, 04 Nov 2020 16:18:04 +0000
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