Patrick Rudolph has uploaded this change for review.
nb/intel/sandybridge/raminit: Fix PDWN_mode on desktops
On desktop boards the PPD bit of MRS register MR0 is set and thus
DLL_Off mode shouldn't be used, as enforced by datasheet
2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.14.1.
Change-Id: Ic42f2ff3e719636be67b00fa37155939cd2e17de
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/22260/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 88357f6..4c7d372 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -3197,7 +3197,14 @@
write32(DEFAULT_MCHBAR + 0x400c, (read32(DEFAULT_MCHBAR + 0x400c) & 0xFFFFCFFF) | 0x1000); // OK
write32(DEFAULT_MCHBAR + 0x440c, (read32(DEFAULT_MCHBAR + 0x440c) & 0xFFFFCFFF) | 0x1000); // OK
- write32(DEFAULT_MCHBAR + 0x4cb0, 0x00000740);
+
+ if (ctrl->mobile)
+ /* APD - DLL Off, 64 DCLKs until idle, decision per rank */
+ write32(DEFAULT_MCHBAR + 0x4cb0, 0x00000740);
+ else
+ /* APD - PPD, 64 DCLKs until idle, decision per rank */
+ write32(DEFAULT_MCHBAR + 0x4cb0, 0x00000340);
+
write32(DEFAULT_MCHBAR + 0x4380, 0x00000aaa); // OK
write32(DEFAULT_MCHBAR + 0x4780, 0x00000aaa); // OK
write32(DEFAULT_MCHBAR + 0x4f88, 0x5f7003ff); // OK
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