Patch Set #1, Line 1:
USB4 is the new hotness. We may want to figure out how to surface that noun since that one is an open standard.
Patch Set #1, Line 30:
These should be using the PCI macros for the registers.
Patch Set #1, Line 31:
1 << 28
256 * MiB
Patch Set #1, Line 33:
resource->gran = 22;
Where did the alignment come from?
Patch Set #1, Line 51:
resource->flags |= IORESOURCE_IO;
It's not clear to me what the rationale is for the resource sizes being speculatively allocated under the device.
Likewise can you please explain why we have to preallocate buses as well? Are you assuming the code running after coreboot cannot allocate buses and mmio spaces?
Patch Set #1, Line 59:
return PCI_SLOT(dev->path.pci.devfn) == 1;
Is this defined in some standard or just happens to be the case for the […]
What does the device tree look like to support this device? I assume this is the router? Are there multiple pci functions with the same did but only one is the router?
Why are we hard coding the number of buses? Shouldn't we make this configurable?
Patch Set #1, Line 93:
.init = 0,
Patch Set #1, Line 94:
.scan_bus = tbt_pciexp_scan_bridge,
I believe thunderbolt and usb4 controllers need to export capabilities in pci config space. Can we not handle the special devices based on that?
Patch Set #1, Line 95:
.enable = 0,
Patch Set #1, Line 102:
move to pci_ids.h
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