Yidi Lin uploaded patch set #34 to the change originally created by CK HU.

View Change

soc/mediatek/mt8192: Switch to highest DDR frequency to reduce bootup time

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Ib37ecc7bf3f1776d27161948e779ed1f96ee9a0c
---
M src/soc/mediatek/mt8192/dramc_dvfs.c
M src/soc/mediatek/mt8192/dramc_pi_main.c
2 files changed, 195 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44730/34

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib37ecc7bf3f1776d27161948e779ed1f96ee9a0c
Gerrit-Change-Number: 44730
Gerrit-PatchSet: 34
Gerrit-Owner: CK HU <ck.hu@mediatek.com>
Gerrit-Reviewer: Duan huayang <huayang.duan@mediatek.com>
Gerrit-Reviewer: Hung-Te Lin <hungte@chromium.org>
Gerrit-Reviewer: Yidi Lin <yidi.lin@mediatek.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: newpatchset