Nico Huber has uploaded this change for review.
soc/intel/cannonlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infracture instead.
Note: Jenkins will fail because somebody has to go through all the dts.
Change-Id: I734262c8191bc217c721c0174d0f844755bc73a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
---
M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
A src/soc/intel/cannonlake/include/soc/pcie.h
A src/soc/intel/cannonlake/pcie_rp.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
11 files changed, 63 insertions(+), 200 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/79918/1
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
index 2269d74..6f0c667 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
@@ -44,31 +44,6 @@
register "PchHdaDspEnable" = "0"
register "PchHdaAudioLinkHda" = "1"
- register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[5]" = "0"
- register "PcieRpEnable[6]" = "0"
- register "PcieRpEnable[7]" = "0"
- register "PcieRpEnable[8]" = "1"
- register "PcieRpEnable[9]" = "1"
- register "PcieRpEnable[10]" = "1"
- register "PcieRpEnable[11]" = "1"
- register "PcieRpEnable[12]" = "0"
- register "PcieRpEnable[13]" = "0"
- register "PcieRpEnable[14]" = "0"
- register "PcieRpEnable[15]" = "0"
- register "PcieRpEnable[16]" = "0"
- register "PcieRpEnable[17]" = "0"
- register "PcieRpEnable[18]" = "0"
- register "PcieRpEnable[19]" = "0"
- register "PcieRpEnable[20]" = "0"
- register "PcieRpEnable[21]" = "0"
- register "PcieRpEnable[22]" = "0"
- register "PcieRpEnable[23]" = "0"
-
register "PcieClkSrcUsage[0]" = "1"
register "PcieClkSrcUsage[1]" = "8"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
@@ -97,30 +72,15 @@
device pci 19.1 off end # I2C #5 (Not available on PCH-H)
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
- device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
+ device ref pcie_rp1 on # x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
- device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
+ device ref pcie_rp5 on # x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on # PCI Express Port 9
+ device ref pcie_rp9 on
register "PcieRpSlotImplemented[8]" = "1"
end
- device pci 1d.4 off end # PCI Express Port 13
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
- device pci 1b.0 off end # PCI Express Port 17
- device pci 1b.1 off end # PCI Express Port 18
- device pci 1b.2 off end # PCI Express Port 19
- device pci 1b.3 off end # PCI Express Port 20
- device pci 1b.4 off end # PCI Express Port 21
- device pci 1b.5 off end # PCI Express Port 22
- device pci 1b.6 off end # PCI Express Port 23
- device pci 1b.7 off end # PCI Express Port 24
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
index b6bf5a8..567e7ef 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
@@ -42,31 +42,6 @@
register "PchHdaDspEnable" = "0"
register "PchHdaAudioLinkHda" = "1"
- register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[5]" = "0"
- register "PcieRpEnable[6]" = "0"
- register "PcieRpEnable[7]" = "0"
- register "PcieRpEnable[8]" = "1"
- register "PcieRpEnable[9]" = "0"
- register "PcieRpEnable[10]" = "0"
- register "PcieRpEnable[11]" = "0"
- register "PcieRpEnable[12]" = "0"
- register "PcieRpEnable[13]" = "0"
- register "PcieRpEnable[14]" = "0"
- register "PcieRpEnable[15]" = "0"
- register "PcieRpEnable[16]" = "1"
- register "PcieRpEnable[17]" = "1"
- register "PcieRpEnable[18]" = "1"
- register "PcieRpEnable[19]" = "1"
- register "PcieRpEnable[20]" = "1"
- register "PcieRpEnable[21]" = "1"
- register "PcieRpEnable[22]" = "1"
- register "PcieRpEnable[23]" = "1"
-
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[1]" = "8"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -105,38 +80,28 @@
device pci 19.1 off end # I2C #5 (Not available on PCH-H)
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
- device pci 1c.0 on # PCI Express Port 1
+ device ref pcie_rp1 on
register "PcieRpSlotImplemented[0]" = "1"
end
- device pci 1c.4 on # PCI Express Port 5
+ device ref pcie_rp5 on
register "PcieRpSlotImplemented[4]" = "1"
end
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on # PCI Express Port 9 x4 SLOT 1
+ device ref pcie_rp9 on # x4 SLOT 1
register "PcieRpSlotImplemented[8]" = "1"
end
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 off end # PCI Express Port 13
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
- device pci 1b.0 on # PCI Express Port 17
+ device ref pcie_rp17 on
register "PcieRpSlotImplemented[16]" = "1"
end
- device pci 1b.1 on # PCI Express Port 18
+ device ref pcie_rp18 on
register "PcieRpSlotImplemented[17]" = "1"
end
- device pci 1b.2 on # PCI Express Port 19
+ device ref pcie_rp19 on
register "PcieRpSlotImplemented[18]" = "1"
end
- device pci 1b.3 on # PCI Express Port 20
+ device ref pcie_rp20 on
register "PcieRpSlotImplemented[19]" = "1"
end
- device pci 1b.4 on # PCI Express Port 21 X4 SLOT 2
+ device ref pcie_rp21 on # x4 SLOT 2
register "PcieRpSlotImplemented[20]" = "1"
end
device pci 1e.1 off end # UART #1
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
index ce46c63..367026f 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
@@ -5,23 +5,6 @@
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHda" = "1"
- register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[5]" = "0"
- register "PcieRpEnable[6]" = "0"
- register "PcieRpEnable[7]" = "0"
- register "PcieRpEnable[8]" = "1"
- register "PcieRpEnable[9]" = "0"
- register "PcieRpEnable[10]" = "0"
- register "PcieRpEnable[11]" = "0"
- register "PcieRpEnable[12]" = "0"
- register "PcieRpEnable[13]" = "0"
- register "PcieRpEnable[14]" = "0"
- register "PcieRpEnable[15]" = "0"
-
register "PcieClkSrcUsage[0]" = "1"
register "PcieClkSrcUsage[1]" = "8"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -82,25 +65,15 @@
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
- device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
+ device ref pcie_rp1 on # x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
- device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
+ device ref pcie_rp5 on # x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on # PCI Express Port 9
+ device ref pcie_rp9 on
register "PcieRpSlotImplemented[8]" = "1"
end
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 off end # PCI Express Port 13
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
index b9fe423..1bf603a 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
@@ -43,23 +43,6 @@
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHda" = "1"
- register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[5]" = "0"
- register "PcieRpEnable[6]" = "0"
- register "PcieRpEnable[7]" = "0"
- register "PcieRpEnable[8]" = "1"
- register "PcieRpEnable[9]" = "0"
- register "PcieRpEnable[10]" = "0"
- register "PcieRpEnable[11]" = "0"
- register "PcieRpEnable[12]" = "0"
- register "PcieRpEnable[13]" = "0"
- register "PcieRpEnable[14]" = "0"
- register "PcieRpEnable[15]" = "0"
-
register "PcieClkSrcUsage[0]" = "1"
register "PcieClkSrcUsage[1]" = "8"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -94,25 +77,15 @@
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
- device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
+ device ref pcie_rp1 on # x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
- device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
+ device ref pcie_rp5 on # x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on # PCI Express Port 9
+ device ref pcie_rp9 on
register "PcieRpSlotImplemented[8]" = "1"
end
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 off end # PCI Express Port 13
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
device pci 1e.1 off end # UART #1
device pci 1f.6 on end # GbE
end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
index 9c08023..415eb46 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
@@ -28,23 +28,6 @@
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHda" = "1"
- register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[5]" = "0"
- register "PcieRpEnable[6]" = "0"
- register "PcieRpEnable[7]" = "0"
- register "PcieRpEnable[8]" = "1"
- register "PcieRpEnable[9]" = "0"
- register "PcieRpEnable[10]" = "0"
- register "PcieRpEnable[11]" = "0"
- register "PcieRpEnable[12]" = "0"
- register "PcieRpEnable[13]" = "0"
- register "PcieRpEnable[14]" = "0"
- register "PcieRpEnable[15]" = "0"
-
register "PcieClkSrcUsage[0]" = "1"
register "PcieClkSrcUsage[1]" = "8"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -78,25 +61,15 @@
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
- device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
+ device ref pcie_rp1 on # x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
- device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
+ device ref pcie_rp5 on # x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on # PCI Express Port 9
+ device ref pcie_rp9 on
register "PcieRpSlotImplemented[8]" = "1"
end
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 off end # PCI Express Port 13
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
device pci 1e.1 off end # UART #1
device pci 1f.6 on end # GbE
end
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 5ae0099..96c0207 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -21,6 +21,7 @@
romstage-y += gspi.c
romstage-y += i2c.c
romstage-y += lpc.c
+romstage-y += pcie_rp.c
romstage-y += pmutil.c
romstage-y += reset.c
romstage-y += spi.c
@@ -39,6 +40,7 @@
ramstage-y += lpc.c
ramstage-y += nhlt.c
ramstage-y += p2sb.c
+ramstage-y += pcie_rp.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
ramstage-y += reset.c
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index a1ba17e..06ef7e5 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -14,23 +14,11 @@
#include <intelblocks/xdci.h>
#include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h>
+#include <soc/pcie.h>
#include <soc/ramstage.h>
#include "chip.h"
-static const struct pcie_rp_group pch_lp_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
- { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 },
- { 0 }
-};
-
-static const struct pcie_rp_group pch_h_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
- { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 },
- { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 },
- { 0 }
-};
-
#if CONFIG(HAVE_ACPI_TABLES)
const char *soc_acpi_name(const struct device *dev)
{
@@ -152,10 +140,7 @@
soc_gpio_pm_configuration();
/* swap enabled PCI ports in device tree if needed */
- if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
- pcie_rp_update_devicetree(pch_h_rp_groups);
- else
- pcie_rp_update_devicetree(pch_lp_rp_groups);
+ pcie_rp_update_devicetree(get_pch_pcie_rp_table());
}
static void cpu_fill_ssdt(const struct device *dev)
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 994f2ae..69a19b5 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -167,7 +167,6 @@
bool PchHdaAudioLinkSndw4;
/* PCIe Root Ports */
- bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
/* PCIe output clocks type to PCIe devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */
diff --git a/src/soc/intel/cannonlake/include/soc/pcie.h b/src/soc/intel/cannonlake/include/soc/pcie.h
new file mode 100644
index 0000000..1ae524d
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/pcie.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_CANNONLAKE_PCIE_H__
+#define __SOC_CANNONLAKE_PCIE_H__
+
+#include <intelblocks/pcie_rp.h>
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void);
+
+#endif /* __SOC_CANNONLAKE_PCIE_H__ */
diff --git a/src/soc/intel/cannonlake/pcie_rp.c b/src/soc/intel/cannonlake/pcie_rp.c
new file mode 100644
index 0000000..4d37841
--- /dev/null
+++ b/src/soc/intel/cannonlake/pcie_rp.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/pcie_rp.h>
+#include <soc/pci_devs.h>
+#include <soc/pcie.h>
+
+static const struct pcie_rp_group pch_lp_rp_groups[] = {
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 },
+ { 0 }
+};
+
+static const struct pcie_rp_group pch_h_rp_groups[] = {
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 },
+ { 0 }
+};
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void)
+{
+ if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
+ return pch_h_rp_groups;
+
+ return pch_lp_rp_groups;
+}
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 737e7c3..c25921f 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -6,11 +6,13 @@
#include <console/console.h>
#include <fsp/util.h>
#include <intelblocks/cpulib.h>
+#include <intelblocks/pcie_rp.h>
#include <intelblocks/pmclib.h>
#include <option.h>
#include <soc/iomap.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
+#include <soc/pcie.h>
#include <soc/romstage.h>
#include <types.h>
@@ -24,7 +26,6 @@
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
unsigned int i;
- uint32_t mask = 0;
m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING));
@@ -52,11 +53,7 @@
m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
m_cfg->RMT = config->RMT;
- for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
- if (config->PcieRpEnable[i])
- mask |= (1 << i);
- }
- m_cfg->PcieRpEnableMask = mask;
+ m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
m_cfg->PrmrrSize = get_valid_prmrr_size();
m_cfg->EnableC6Dram = config->enable_c6dram;
#if CONFIG(SOC_INTEL_COMETLAKE)
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