awokd@danwin1210.me has uploaded this change for review.

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vc/amd/agesa/f16kb: Fix out of bounds read

ByteLane is incorrectly used unitialized from prior for statement.
Found nothing in following code that attempted to reference
PassTestRxEnDly at that index, so appears safe to delete.
Additionally, found nothing following with the
OutOfRange[ByteLane]==TRUE condition that would expect
'PassTestRxEnDly[ByteLane] = RxOrig[ByteLane];'.

Change-Id: Icd18a146aba6b6120d37518d8c40c7efbc05afa3
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241804
---
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
1 file changed, 0 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36192/1

diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
index ce295ac..caf8f51 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -314,7 +314,6 @@
       //
       IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t Setting PassTestRxEnDly\n");
       IDS_HDT_CONSOLE (MEM_FLOW, "\t  PassTestRxEnDly: ");
-      PassTestRxEnDly[ByteLane] = RxOrig[ByteLane];
       for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
         if (RxEnDlyTargetFound[ByteLane] == FALSE) {
           // Calculate "PassTestRxEnDly" from  current "RxEnDly"

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