Subrata Banik has uploaded this change for review.

View Change

soc/intel/common/timer: Fix cosmetic errors as per CB:35148 review

BUG=b:139798422, b:129839774
TEST=Able to build and boot KBL/CML/ICL.

Change-Id: I341eec13d275504545511904db0acd23ad34e940
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/common/block/timer/timer.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/35234/1

diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c
index 8fde541..70072cc 100644
--- a/src/soc/intel/common/block/timer/timer.c
+++ b/src/soc/intel/common/block/timer/timer.c
@@ -38,7 +38,7 @@
 
 static unsigned long get_hardcoded_crystal_freq(void)
 {
-	unsigned int core_crystal_nominal_freq_khz;
+	unsigned long core_crystal_nominal_freq_khz = 0;
 
 	/*
 	 * Denverton SoCs don't report crystal clock, and also don't support
@@ -70,7 +70,7 @@
  */
 static unsigned long calculate_tsc_freq_from_core_crystal(void)
 {
-	unsigned int core_crystal_nominal_freq_khz;
+	unsigned long core_crystal_nominal_freq_khz;
 	struct cpuid_result cpuidr_15h;
 
 	if (get_max_cpuid_func() < 0x15)

To view, visit change 35234. To unsubscribe, or for help writing mail filters, visit settings.