Yidi Lin has uploaded this change for review.

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soc/mediatek/mt8192: Load MCUPM firmware and boot up MCUPM.

Change-Id: I50bea1942507b4a40df9730b4e1bf98980d74277
---
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/mcupm.h
M src/soc/mediatek/mt8192/include/soc/memlayout.ld
A src/soc/mediatek/mt8192/mcupm.c
M src/soc/mediatek/mt8192/soc.c
6 files changed, 57 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46392/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 9bb9cfd..59d105c 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -41,6 +41,7 @@
ramstage-y += ../common/mmu_operations.c mmu_operations.c
ramstage-y += ../common/mtcmos.c mtcmos.c
ramstage-y += soc.c
+ramstage-y += mcupm.c
ramstage-y += ../common/timer.c
ramstage-y += ../common/uart.c
ramstage-y += ../common/usb.c usb.c
@@ -52,6 +53,11 @@
spm_firmware.bin-type := raw
spm_firmware.bin-compression := $(CBFS_COMPRESS_FLAG)

+cbfs-files-y += mcupm.bin
+mcupm.bin-file := $(MT8192_BLOB_DIR)/mcupm.bin
+mcupm.bin-type := raw
+mcupm.bin-compression := $(CBFS_COMPRESS_FLAG)
+
DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram
$(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf
$(DRAM_CBFS)-type := stage
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h
index 9760c88..9864e5b 100755
--- a/src/soc/mediatek/mt8192/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h
@@ -5,6 +5,8 @@

enum {
MCUSYS_BASE = 0x0C530000,
+ MCUPM_SRAM_BASE = 0x0C540000,
+ MCUPM_CFG_BASE = 0x0C560000,
IO_PHYS = 0x10000000,
};

diff --git a/src/soc/mediatek/mt8192/include/soc/mcupm.h b/src/soc/mediatek/mt8192/include/soc/mcupm.h
new file mode 100644
index 0000000..dcb8c4a
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/mcupm.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8192_MCUPM_H
+#define SOC_MEDIATEK_MT8192_MCUPM_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8192_mcupm_regs {
+ u32 sw_rstn;
+};
+static struct mt8192_mcupm_regs *const mt8192_mcupm = (void *)MCUPM_CFG_BASE;
+void mcupm_init(void);
+#endif /* SOC_MEDIATEK_MT8192_MCUPM_H */
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
index df9d376..3bef5b1 100644
--- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
@@ -37,7 +37,7 @@

DRAM_START(0x40000000)
POSTRAM_CBFS_CACHE(0x40000000, 2M)
- RAMSTAGE(0x40200000, 256K)
+ RAMSTAGE(0x40200000, 512K)

BL31(0x54600000, 0x60000)
}
diff --git a/src/soc/mediatek/mt8192/mcupm.c b/src/soc/mediatek/mt8192/mcupm.c
new file mode 100644
index 0000000..88efc85
--- /dev/null
+++ b/src/soc/mediatek/mt8192/mcupm.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/barrier.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/mcupm.h>
+#include <string.h>
+
+#define BUF_SIZE (128 * KiB)
+static uint8_t mcupm_bin[BUF_SIZE] __aligned(8);
+
+void mcupm_init(void)
+{
+ const char *file_name = "mcupm.bin";
+ size_t fw_size = cbfs_boot_load_file(file_name,
+ mcupm_bin,
+ sizeof(mcupm_bin),
+ CBFS_TYPE_RAW);
+
+ if (fw_size == 0) {
+ die("MCUPM file :mcupm.bin not found.");
+ }
+
+ write32(&mt8192_mcupm->sw_rstn, 0x0);
+ write32((void *)(0x0C55FAA0), 0x0);
+ memcpy((void *)MCUPM_SRAM_BASE, mcupm_bin, fw_size);
+ /* Memory barrier to ensure that all fw code is loaded
+ before we release the reset pin. */
+ mb();
+ write32(&mt8192_mcupm->sw_rstn, 0x1);
+}
diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c
index 6978406..6deb833 100644
--- a/src/soc/mediatek/mt8192/soc.c
+++ b/src/soc/mediatek/mt8192/soc.c
@@ -4,6 +4,7 @@
#include <soc/emi.h>
#include <soc/mmu_operations.h>
#include <symbols.h>
+#include <soc/mcupm.h>

static void soc_read_resources(struct device *dev)
{
@@ -13,6 +14,7 @@
static void soc_init(struct device *dev)
{
mtk_mmu_disable_l2c_sram();
+ mcupm_init();
}

static struct device_operations soc_ops = {

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I50bea1942507b4a40df9730b4e1bf98980d74277
Gerrit-Change-Number: 46392
Gerrit-PatchSet: 1
Gerrit-Owner: Yidi Lin <yidi.lin@mediatek.com>
Gerrit-Reviewer: Julius Werner <jwerner@chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-MessageType: newchange