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3 comments:

• File Documentation/mainboard/libretrend/lt1000.md:

  • Patch Set #13, Line 47: Fastboot

    what data is missing that prevents this from working?

    I maybe lack information about:

    • DqByteMapCh0/1
    • DqsMapCpu2DramCh0/1

    and what FSP does about it. I don't know how much the DQ/DQS to CPU mapping matters. The mainboard has two DIMM slots, but not passing SPD results in error in MemoryInit. KBL FSP does not have any fields to indicate "it is a DIMM, get the SPD over SMBUS" orsomething like that.

    For example, if I put a DDR4 into DIMM1 slot, after booting from S5, the memory is retrained and new MRC cache is produced. What is more, one mainboard that I have, always reproduces this issue while the second one, wherever I put the DIMM, the fastboot always works even when put into S5 or G3...

  • Patch Set #13, Line 62: - speakers and mic header

    System 76's coreboot-collector app does a nice job of dumping codecs (and GPIOs) from Linux: […]

    Thank you Matt.

• File src/mainboard/libretrend/lt1000/bootblock.c:

  • Patch Set #13, Line 42: */

    What about port 2?

    Port 2 by default has IOBASE = 0x2f8 after reset, so it is not colliding

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