[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Update Flex Ratio from MSR

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21864

Change subject: soc/intel/cannonlake: Update Flex Ratio from MSR
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soc/intel/cannonlake: Update Flex Ratio from MSR

Read back from MSR to apply Flex Ratio into FSP.

TEST=Apply the patch and test to be able to boot up into OS.

Change-Id: Iadd4068bd7076b2f097ffe2e2ed87520b9c4c809
Signed-off-by: Lijian Zhao 
---
M src/soc/intel/cannonlake/romstage/romstage.c
1 file changed, 14 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21864/1

diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 1775cae..466885a 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -18,11 +18,13 @@
 #include <assert.h>
 #include <chip.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <fsp/util.h>
 #include <intelblocks/pmclib.h>
 #include <memory_info.h>
+#include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
@@ -66,6 +68,16 @@
    run_postcar_phase(&pcf);
 }

+static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
+{
+	msr_t flex_ratio;
+	/*
+	 * Set cpuratio to that value to intended flex ratio.
+	 */
+	flex_ratio = rdmsr(MSR_FLEX_RATIO);
+	m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
+}
+
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 {
    unsigned int i;
@@ -86,8 +98,8 @@
    m_cfg->PcieRpEnableMask = mask;
    m_cfg->PrmrrSize = config->PrmrrSize;
    m_cfg->EnableC6Dram = config->enable_c6dram;
-	/* Disable Cpu Ratio Override temporary. */
-	m_cfg->CpuRatio = 0;
+
+	cpu_flex_override(m_cfg);
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)