Tim Wawrzynczak submitted this change.
mb/google/volteer/var/elemi: Update gpio and devicetree
Update gpio and devicetree for elemi.
BUG=b:170604353
TEST=emerge-volteer coreboot and boot into kernel
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I5b8880d485ed73aa4e65c1249c58f02c8f0c6501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
M src/mainboard/google/volteer/variants/elemi/Makefile.inc
A src/mainboard/google/volteer/variants/elemi/gpio.c
M src/mainboard/google/volteer/variants/elemi/overridetree.cb
3 files changed, 357 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc
index 9064208..b0bfc56 100644
--- a/src/mainboard/google/volteer/variants/elemi/Makefile.inc
+++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc
@@ -1,3 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += gpio.c
+
romstage-y += memory.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/volteer/variants/elemi/gpio.c b/src/mainboard/google/volteer/variants/elemi/gpio.c
new file mode 100644
index 0000000..6868aca
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/elemi/gpio.c
@@ -0,0 +1,224 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+ /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
+ PAD_CFG_GPO(GPP_A7, 1, DEEP),
+ /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
+ PAD_CFG_GPO(GPP_A8, 0, DEEP),
+ /* A10 : I2S2_RXD ==> EN_SPKR_PA */
+ PAD_CFG_GPO(GPP_A10, 1, DEEP),
+ /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
+ PAD_CFG_GPO(GPP_A13, 1, DEEP),
+ /* A16 : USB_OC3# ==> USB_C0_OC_ODL */
+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+ /* A18 : DDSP_HPDB ==> HDMI_HPD */
+ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+ /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
+ PAD_CFG_GPO(GPP_A21, 1, DEEP),
+ /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
+ PAD_CFG_GPO(GPP_A22, 1, DEEP),
+ /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
+ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
+
+ /* B2 : VRALERT# ==> EN_PP3300_SSD */
+ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+ /* B3 : CPU_GP2 ==> PEN_DET_ODL */
+ PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+ /* B4 : CPU_GP3==> EN_PP3300_EMMC */
+ PAD_CFG_GPO(GPP_B4, 1, DEEP),
+ /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+ /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+ /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+ /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+ /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
+ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+ /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
+ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+ /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
+ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+
+ /* C0 : SMBCLK ==> EN_PP3300_WLAN */
+ PAD_CFG_GPO(GPP_C0, 1, DEEP),
+ /* C1 : SMBCLK ==> EMMC_CLKREQ_ODL*/
+ PAD_CFG_GPO(GPP_C1, 1, DEEP),
+ /* C2 : SMBALERT# ==> GPP_C2_STRAP */
+ PAD_NC(GPP_C2, DN_20K),
+ /* C3 : EMMC_PE_WAKE_ODL*/
+ PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+ /* C4 : EMMC_PERST_L*/
+ PAD_CFG_GPO(GPP_C4, 1, DEEP),
+
+ /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP_0 */
+ PAD_NC(GPP_C5, DN_20K),
+ /* C10 : UART0_RTS# ==> USI_RST_L */
+ PAD_CFG_GPO(GPP_C10, 0, DEEP),
+ /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+ /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+ /* C20 : UART2_RXD ==> FPMCU_INT_L */
+ PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL),
+ /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+ PAD_CFG_GPO(GPP_C22, 0, DEEP),
+ /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
+ PAD_CFG_GPO(GPP_C23, 1, DEEP),
+
+ /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+ /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */
+ /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+ /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */
+ PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7),
+ /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
+ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+ /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
+ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+ /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
+ PAD_CFG_GPO(GPP_D16, 1, DEEP),
+ /* D17 : ISH_GP4 ==> EN_FCAM_PWR */
+ PAD_CFG_GPO(GPP_D17, 1, DEEP),
+
+ /* E1 : SPI1_IO2 ==> PEN_DET_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
+ /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+ /* E3 : CPU_GP0 ==> USI_REPORT_EN */
+ PAD_CFG_GPO(GPP_E3, 0, DEEP),
+ /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+ /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */
+ PAD_CFG_GPI(GPP_E6, NONE, DEEP),
+ /* E7 : CPU_GP1 ==> USI_INT */
+ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
+ /* E8 : SPI1_CS1# ==> SLP_S0IX */
+ PAD_CFG_GPO(GPP_E8, 0, DEEP),
+ /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+ /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
+ PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
+ /* E18 : DDP1_CTRLCLK ==> NC */
+ PAD_NC(GPP_E18, NONE),
+ /* E20 : DDP2_CTRLCLK ==> NC */
+ PAD_NC(GPP_E20, NONE),
+ /* E21 : DDP2_CTRLDATA ==> NC */
+ PAD_NC(GPP_E21, NONE),
+
+ /* F7 : GPPF7_STRAP ==> GPP_F7_STRAP */
+ PAD_NC(GPP_F7, DN_20K),
+ /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */
+ PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH),
+ /* F11 : THC1_SPI2_CLK ==> NC */
+ PAD_NC(GPP_F11, NONE),
+ /* F12 : GSXDOUT ==> NC */
+ PAD_NC(GPP_F12, NONE),
+
+ /* F13 : GSXDOUT ==> WiFi_DISABLE_L */
+ PAD_CFG_GPO(GPP_F13, 1, DEEP),
+ /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */
+ PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
+
+ /* H0 : GPPH0_BOOT_STRAP1 */
+ PAD_NC(GPP_H0, DN_20K),
+ /* H1 : GPPH1_BOOT_STRAP2 */
+ PAD_NC(GPP_H1, DN_20K),
+ /* H2 : GPPH2_BOOT_STRAP3 */
+ PAD_NC(GPP_H2, DN_20K),
+ /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
+ PAD_CFG_GPO(GPP_H3, 1, DEEP),
+ /* H10 : SRCCLKREQ4# */
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+ /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
+ PAD_CFG_GPO(GPP_H11, 1, DEEP),
+ /* H16 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
+ PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
+ /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
+ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+ /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */
+ PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+
+ /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+ /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
+ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+ /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
+ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+ /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
+ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+ /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
+ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
+ /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
+ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+ /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
+ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+
+ /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */
+ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
+ /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */
+ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
+ /* S6 : SNDW3_CLK ==> DMIC_CLK0 */
+ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+ /* S7 : SNDW3_DATA ==> DMIC_DATA0 */
+ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+
+ /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
+ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+ /* A17 : DDSP_HPDC ==> MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+
+ /* B11 : PMCALERT# ==> PCH_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+ /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
+ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
+
+ /* C0 : SMBCLK ==> EN_PP3300_WLAN */
+ PAD_CFG_GPO(GPP_C0, 1, DEEP),
+ /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+ /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+ PAD_CFG_GPO(GPP_C22, 0, DEEP),
+
+ /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
+ PAD_CFG_GPO(GPP_D16, 1, DEEP),
+
+ /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
+ PAD_CFG_GPO(GPP_H11, 1, DEEP),
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(override_gpio_table);
+ return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb
index 31e1927..5ea48ad 100644
--- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb
@@ -1,5 +1,49 @@
chip soc/intel/tigerlake
+ register "TcssAuxOri" = "1"
+ register "DdiPort1Hpd" = "0"
+ register "DdiPort2Hpd" = "0"
+ register "IomTypeCPortPadCfg[0]" = "0x090E000A"
+ register "IomTypeCPortPadCfg[1]" = "0x090E000D"
+
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| GSPI1 | Fingerprint MCU |
+ #| I2C0 | Audio |
+ #| I2C1 | Touchscreen |
+ #| I2C2 | WLAN, SAR0 |
+ #| I2C3 | Camera, SAR1 |
+ #| I2C5 | Trackpad |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
+
device domain 0 on
device ref north_xhci on
chip drivers/usb/acpi
@@ -76,6 +120,90 @@
end
end
end
+ device ref i2c0 on
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5682""
+ register "name" = ""RT58""
+ register "desc" = ""Headset Codec""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)"
+ # Set the jd_src to RT5668_JD1 for jack detection
+ register "property_count" = "1"
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on end
+ end
+ end
+ device ref i2c1 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""GTCH7503""
+ register "generic.desc" = ""G2TOUCH Touchscreen""
+ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+ register "generic.probed" = "1"
+ register "generic.reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+ register "generic.reset_delay_ms" = "50"
+ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
+ register "generic.enable_delay_ms" = "1"
+ register "generic.has_power_resource" = "1"
+ register "generic.disable_gpio_export_in_crs" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 40 on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+ register "probed" = "1"
+ register "reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+ register "reset_delay_ms" = "100"
+ register "reset_off_delay_ms" = "5"
+ register "has_power_resource" = "1"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
+ register "enable_delay_ms" = "10"
+ register "enable_off_delay_ms" = "1"
+ device i2c 10 on end
+ end
+ end
+ device ref i2c5 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
+ register "wake" = "GPE0_DW2_15"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
+ end
+ device ref hda on
+ chip drivers/generic/max98357a
+ register "hid" = ""MX98357A""
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
+ register "sdmode_delay" = "5"
+ device generic 0 on end
+ end
+ end
+ device ref pmc hidden
+ # The pmc_mux chip driver is a placeholder for the
+ # PMC.MUX device in the ACPI hierarchy.
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "9"
+ register "usb3_port_number" = "1"
+ # SBU & HSL follow CC
+ device generic 0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "4"
+ register "usb3_port_number" = "2"
+ # SBU is fixed, HSL follows CC
+ register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+ device generic 1 on end
+ end
+ end
+ end
+ end # PMC
end
-
end
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