Angel Pons has uploaded this change for review.

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[UNTESTED] sb/intel/bd82x6x: Fix replay issues

Rewrite suspicious register handling as per reference code. Proper
handling of the value in the RPC register needs some IOBP operations,
and will be done in a follow-up once `pch_iobp_update` can be used.

Change-Id: I40c7eb2323c22185ca8184166b3ca225c61e9299
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/southbridge/intel/bd82x6x/early_pch.c
1 file changed, 23 insertions(+), 23 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/49165/1

diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 767d3ad..6daafe0 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -16,8 +16,6 @@
 #include "pch.h"
 #include "chip.h"
 
-#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
-
 static void wait_iobp(void)
 {
 	while (RCBA8(IOBPS) & 1)
@@ -67,13 +65,17 @@
 
 void early_pch_init_native_dmi_post(void)
 {
-	RCBA32(CIR0);	// !!! = 0x01200654
-	RCBA32(CIR0) = 0x01200654;
-	RCBA32(CIR0);	// !!! = 0x01200654
-	RCBA32(CIR0) = 0x012a0654;
-	RCBA32(CIR0);	// !!! = 0x012a0654
-	RCBA8(UPDCR);	// !!! = 0x00
-	RCBA8(UPDCR) = 0x05;
+	u32 reg32;
+
+	reg32 = RCBA32(CIR0);
+	reg32 &= ~(0xff << 16 | 0xfff);
+	reg32 |= 0x654;		/* Set the recommended TC encoding */
+	reg32 |= 0x20 << 16;
+	reg32 |= 0x0a << 16;	/* VCp enabled */
+	RCBA32(CIR0) = reg32;
+	RCBA32(CIR0);		/* Read back for posted write to take effect */
+
+	RCBA8(UPDCR) = RCBA8(UPDCR) | 1 << 2 | 1 << 0;
 
 	/*
 	 * Virtual Channel resources must match settings in DMIBAR!
@@ -135,23 +137,21 @@
 
 void early_pch_init_native(void)
 {
-	pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2);
+	/* Lock down PMBASE */
+	pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, 1 << 1);
 
-	RCBA32(CIR1) = 0x00109000;
-	RCBA32(REC); // !!! = 0x00000000
-	RCBA32(REC) = 0x40000000;
+	RCBA32(CIR1) = 0x00109000;	/* Mask some errors */
+	RCBA32_OR(REC, 1 << 30);
 	RCBA32(0x100c) = 0x01110000;
-	RCBA8(0x2340) = 0x1b;
-	RCBA32(CIR6); // !!! = 0x0a080000
-	RCBA32(CIR6) = 0x0a280000;
-	RCBA32(0x2310); // !!! = 0xc809605b
-	RCBA32(0x2310) = 0xa809605b;
+	RCBA8(0x2340) = 0x1b;		/* Set Gen 1 Common Clock N_FTS */
+	RCBA32_OR(CIR6, 1 << 21);
+	RCBA32_AND_OR(0x2310, ~(3 << 29), 1 << 29);
 	RCBA32(DMC2) = 0x00854c74;
-	RCBA8(RPC);  // !!! = 0x00
-	RCBA32(0x2310); // !!! = 0xa809605b
-	RCBA32(0x2310) = 0xa809605b;
-	RCBA32(0x2310); // !!! = 0xa809605b
-	RCBA32(0x2310) = 0xa809605b;
+
+	/* TODO: Handle non-zero cases */
+	RCBA8(RPC);
+	RCBA32_AND_OR(0x2310, ~(3 << 22), 0);
+	RCBA32_AND_OR(0x2310, ~(3 << 20), 0);
 
 	write_iobp(0xea007f62, 0x00590133);
 	write_iobp(0xec007f62, 0x00590133);

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