[coreboot-gerrit] [M] Change in coreboot[main]: soc/amd/common/acpi: Add SPI flash controller

[Ana Carolina Cabral (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier.

Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84918?usp=email )

Change subject: soc/amd/common/acpi: Add SPI flash controller
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soc/amd/common/acpi: Add SPI flash controller

Add the ACPI code for the flash SPI controller.

Change-Id: I0f2c1e3351671ad47fbe5c890e4f99d2e19dbfbf
Signed-off-by: Ana Carolina Cabral 
---
A src/soc/amd/common/acpi/spi.asl
1 file changed, 72 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/84918/1

diff --git a/src/soc/amd/common/acpi/spi.asl b/src/soc/amd/common/acpi/spi.asl
new file mode 100644
index 0000000..6a5e0a3
--- /dev/null
+++ b/src/soc/amd/common/acpi/spi.asl
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/spi_defs.h>
+
+  Mutex (ASM1, 0) //Amd Spi1 Semaphore Mutex
+  Name (SVBF, Buffer (0x100) {0})
+  CreateWordField(SVBF, 0x014, RG22)
+  CreateDWordField(SVBF, 0x018, SAR2)
+#include <soc/iomap.h>
+
+Device(SPI1) {  // SPI controller
+    Name(_HID, "AMDI0062")
+    Name(_UID, 0)
+
+    Method (_STA, 0, NotSerialized) {
+        Return (0x0f)
+    } // end of Method _STA
+    OperationRegion(SPIM, SystemMemory, SPI_BASE_ADDRESS , 0x100)  // SPI Mmio Register
+    Field(SPIM, AnyAcc, NoLock, Preserve) {
+      Offset (0x1D),
+      ASCE,2,  // AltSpiCsEn
+      Offset (SPI100_SPEED_CONFIG),
+      SSSC, 16,  // SPIx22 SPI100 Speed Config
+      Offset (SPI_MISC_CNTRL),
+      STRN,1,  // Spi TuRN
+      , 2,
+      BOWS,1,  //Bios OWnerShip
+      DOWS,1,  //Driver OWnerShip
+    }
+
+    Method (_CRS, 0x0, NotSerialized) {
+      Name (RBUF, ResourceTemplate () {
+        Memory32Fixed(ReadWrite, 0xFEC10000, 0x100)
+      }) // End of Name (RBUF
+      Return (RBUF)
+    } // End of Method _CRS
+
+    Method(ASSC, 2, Serialized) //Amd Spi Semaphore Control Arg0:Request ID  Arg1:Timeout in Micro Second
+    {
+      Acquire (ASM1, 0xFFFF)
+      Store (Arg1, Local0) //save timeout
+      Switch (ToInteger(Arg0))
+      {
+        Case (3) //Driver Acquire Spi Bus
+          {
+            store (one, DOWS)
+            store (one, STRN)
+            while (LAnd(BOWS,STRN)) {
+              if (Arg1) {
+                stall (1)
+                Subtract (Local0, one, Local0)
+                if (LEqual(Local0, zero)) { Break }
+              }
+            }
+            //store (RAR2, SAR2) //TODO SPI_ENTRY
+            //store (zero,RAR2) //TODO SPI_ENTRY
+            store (2, ASCE)
+            store (SSSC, RG22)
+          }
+        Case (4) //Driver Release Spi Bus
+          {
+            store (RG22, SSSC)
+            store (zero, ASCE)
+            //store (SAR2, RAR2)//TODO SPI_ENTRY
+            store (one, Local0)
+            store (zero, DOWS)
+          }
+      }
+      Release (ASM1)
+      Return (Local0)
+    }
+  } // End Device SPI1
\ No newline at end of file