Pavan Holla has uploaded this change for review.

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Hide typec ACPI device if UCSI is supported

We need to remove the ACPI table entry associated with the cros_ec_typec
driver once we switch to the UCSI kernel driver. The logic to remove the
ACPI device is

1) Check if EC implements a PPM using a feature flag.
2) During the transition to the new kernel driver, check if CBI flag to
enable UCSI is set.

b/333074788 and https://crrev.com/c/5421069 track the corresponding EC
change to add CBI.
https://crrev.com/c/5416841 is the change for adding the feature flag

BUG=b:333078787
TEST=emerge-brox coreboot chromeos-bootimage
BRANCH=none

Change-Id: I67dff6445aa7ba3ba48a04d1df3541f880d09d0a
Signed-off-by: Pavan Holla <pholla@google.com>
---
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec.h
M src/ec/google/chromeec/ec_acpi.c
3 files changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/81967/1

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 8fdfbfb..43f906a 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -723,6 +723,30 @@
 	return cbi_get_uint32(ssfc, CBI_TAG_SSFC);
 }
 
+int google_chromeec_get_ucsi_enabled(bool *ucsi_enabled)
+{
+	int rv;
+	uint32_t cc = 0;
+
+	*ucsi_enabled = false;
+
+	rv = google_chromeec_check_feature(EC_FEATURE_UCSI_PPM);
+	if (rv <= 0) {
+		printk(BIOS_INFO, "Cannot check whether EC_FEATURE_UCSI_PPM is available.\n");
+		return rv;
+	}
+
+	/* Check if PPM is disabled at runtime. */
+	rv = cbi_get_uint32(&cc, CBI_TAG_COMMON_CONTROL);
+	if (rv < 0) {
+		printk(BIOS_INFO, "Cannot get tag CBI_TAG_COMMON_CONTROL from CBI.\n");
+		return rv;
+	}
+
+	*ucsi_enabled = ((cc & CBI_COMMON_CONTROL_UCSI_ENABLED) != 0);
+	return 0;
+}
+
 static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag)
 {
 	struct ec_params_get_cbi params = {
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 0e1df9c..3567bf3 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -425,6 +425,17 @@
 bool google_chromeec_is_battery_present_and_above_critical_threshold(void);
 
 #if CONFIG(HAVE_ACPI_TABLES)
+
+#define CBI_COMMON_CONTROL_UCSI_ENABLED 0x01
+
+/**
+ * Determine if the UCSI stack is currently active.
+ *
+ * @param ucsi_enabled	Set to true if EC implements the UCSI stack
+ * @return		0 on success, -1 on error
+ */
+int google_chromeec_get_ucsi_enabled(bool *ucsi_enabled);
+
 /**
  * Writes USB Type-C PD related information to the SSDT
  *
diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c
index cf29636..99451df 100644
--- a/src/ec/google/chromeec/ec_acpi.c
+++ b/src/ec/google/chromeec/ec_acpi.c
@@ -150,6 +150,7 @@
 	struct ec_google_chromeec_config *config = dev->chip_info;
 	int rv;
 	int i;
+	bool ucsi_enabled = false;
 	unsigned int num_ports = 0;
 	struct device *usb2_port;
 	struct device *usb3_port;
@@ -157,6 +158,13 @@
 	struct acpi_pld pld = {0};
 	uint32_t pcap_mask = 0;
 
+	/* UCSI implementations do not require an ACPI device
+	 * with mux info since the linux kernel doesn't set
+	 * the muxes. */
+	rv = google_chromeec_get_ucsi_enabled(&ucsi_enabled);
+	if (rv == 0 && ucsi_enabled)
+		return;
+
 	rv = google_chromeec_get_num_pd_ports(&num_ports);
 	if (rv || num_ports == 0)
 		return;

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