HAOUAS Elyes has uploaded this change for review.

View Change

sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register

Change-Id: I779387fb0c9d3ad6e16d4ccfc39c38dfe6620345
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/southbridge/amd/cimx/sb800/late.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/40806/1

diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index e4a1795..0993d2d 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -99,7 +99,7 @@
 	}
 
 	dev->command |= PCI_COMMAND_MASTER;
-	pci_write_config8(dev, PCI_COMMAND, dev->command);
+	pci_write_config16(dev, PCI_COMMAND, dev->command);
 	printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n");
 }
 

To view, visit change 40806. To unsubscribe, or for help writing mail filters, visit settings.