Attention is currently required from: Shreesh Chhabbi.
Shreesh Chhabbi would like Shreesh Chhabbi to review this change.
mb/google/volteer: Enable External Bypass, ClkGate & PhyGate
Sets the soc config options for ExternalBypass, ExternalClkGate and
ExternalPhyGate. These are used to enable or disable respective S0ix
substates.
BUG=b:177821896
TEST=Build coreboot for volteer
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/50290/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index d74476a..0bbcdba 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -250,6 +250,15 @@
# Enable DPTF
register "dptf_enable" = "1"
+
+ # Enable External Bypass
+ register "ExternalBypass" = "1"
+
+ # Enable External Clk Gate
+ register "ExternalClkGated" = "1"
+
+ # Enable External Phy Gate
+ register "ExternalPhyGated" = "1"
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
.tdp_pl1_override = 15,
To view, visit change 50290. To unsubscribe, or for help writing mail filters, visit settings.