CK HU would like Duan huayang to review this change.

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soc/mediatek/mt8192: Do dramc after calibration settings

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Id90219ca0be83ecb6342480a9692820462d9ae9d
---
M src/soc/mediatek/mt8192/dramc_pi_basic_api.c
M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
M src/soc/mediatek/mt8192/dramc_pi_main.c
3 files changed, 58 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/44725/1

diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
index d418228..ab6b027 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
@@ -4893,6 +4893,38 @@
 	SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSC_CALEN, 1);
 }
 
+void enable_write_DBI_after_calibration(const struct ddr_cali* cali)
+{
+	struct mr_values *mr_value = cali->mr_value;
+
+	for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++)
+		for (u8 rk = RANK_0; rk < cali->support_ranks; rk++)
+			for (u8 fsp = FSP_0; fsp < FSP_MAX; fsp++) {
+				u8 mr13 = mr_value->mr13[rk];
+				u8 mr03 = mr_value->mr03[fsp];
+
+				mr13 = (mr13 & ~ BIT(6)) | (fsp << 6);
+				dramc_mode_reg_write_by_rank(cali, chn, rk, 13, mr13);
+				mr03 = (mr03 & ~ BIT(7)) | (cali->w_dbi[fsp] << 7);
+				dramc_mode_reg_write_by_rank(cali, chn, rk, 3, mr03);
+
+				mr_value->mr13[rk] = mr13;
+				mr_value->mr03[fsp] = mr03;
+			}
+}
+
+void dramc_set_mr13_vrcg_to_normal(const struct ddr_cali* cali)
+{
+	struct mr_values *mr_value = cali->mr_value;
+
+	for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++)
+		for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) {
+			u8 mr13 = mr_value->mr13[rk] & ~ BIT(3);
+			dramc_mode_reg_write_by_rank(cali, chn, rk, 13, mr13);
+			mr_value->mr13[rk] = mr13;
+		}
+}
+
 void apply_write_dbi_power_improve(bool en)
 {
 	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
index 2082f4d..9fee4d1 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
@@ -3014,3 +3014,26 @@
 	SET32_BITFIELDS(&ch[chn].ao.shu_dqsosc_set0,
 		SHU_DQSOSC_SET0_DQSOSCENCNT, dqsosc_en_cnt);
 }
+
+void after_calib(const struct ddr_cali* cali)
+{
+	enable_write_DBI_after_calibration(cali);
+	dramc_set_mr13_vrcg_to_normal(cali);
+	cke_fix_onoff(cali, CHANNEL_A, RANK_MAX, CKE_DYNAMIC);
+	cke_fix_onoff(cali, CHANNEL_B, RANK_MAX, CKE_DYNAMIC);
+
+	for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) {
+		SET32_BITFIELDS(&ch[chn].ao.dummy_rd,
+			DUMMY_RD_RANK_NUM, cali->support_ranks);
+		SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl7,
+			MISC_CG_CTRL7_CK_BFE_DCM_EN, 0);
+		SET32_BITFIELDS(&ch[chn].ao.test2_a4,
+			TEST2_A4_TESTAGENTRKSEL, 4);
+		SET32_BITFIELDS(&ch[chn].ao.test2_a2,
+			TEST2_A2_TEST2_OFF, 0x20);
+		SET32_BITFIELDS(&ch[chn].phy_ao.misc_dutyscan1,
+			MISC_DUTYSCAN1_DQSERRCNT_DIS, 0);
+		SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1,
+			MISC_CTRL1_R_DMSTBENCMP_RK_OPT, 0);
+	}
+}
diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c
index c3c19bf..2bcc449 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_main.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_main.c
@@ -437,5 +437,8 @@
 		dramc_info("frequency %d calibration finish\n", get_frequency(&cali));
 	}
 
+	after_calib(&cali);
+	enable_dfs_hw_mode_clk();
+
 	dramc_runtime_config(&cali);
 }

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