[coreboot-gerrit] [M] Change in coreboot[master]: mb/amd/mayan/port_descriptors.c: Update DXIO for mayan

[Fred Reitberger (Code Review)]

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70214 )

Change subject: mb/amd/mayan/port_descriptors.c: Update DXIO for mayan
......................................................................

mb/amd/mayan/port_descriptors.c: Update DXIO for mayan

Update DXIO descriptors for mayan per schematic 105-D59700-00A Rev 1.00

Signed-off-by: Fred Reitberger 
Change-Id: If1aca5423879433c1d0d2405d96cf7d806c57b20
---
M src/mainboard/amd/mayan/port_descriptors.c
1 file changed, 90 insertions(+), 29 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/70214/1

diff --git a/src/mainboard/amd/mayan/port_descriptors.c b/src/mainboard/amd/mayan/port_descriptors.c
index 151ad14..a22e6df 100644
--- a/src/mainboard/amd/mayan/port_descriptors.c
+++ b/src/mainboard/amd/mayan/port_descriptors.c
@@ -6,48 +6,97 @@
 #include <soc/platform_descriptors.h>
 #include <types.h>

-/* TODO: Update for mayan */
-
 static const fsp_dxio_descriptor mayan_dxio_descriptors[] = {
-	{
+	{ /* MXM */
    	.engine_type = PCIE_ENGINE,
    	.port_present = true,
    	.start_logical_lane = 0,
-		.end_logical_lane = 0,
-		.device_number = 2,
+		.end_logical_lane = 3,
+		.device_number = 1,
    	.function_number = 1,
    	.link_speed_capability = GEN3,
    	.turn_off_unused_lanes = true,
-		.link_aspm = 2,
-		.link_hotplug = 3,
-		.clk_req = CLK_REQ3,
+		.link_aspm = ASPM_L1,
+		.link_hotplug = 0,
+		.clk_req = CLK_REQ0,
    },
-	{
+	{ /* NVMe SSD0 */
    	.engine_type = PCIE_ENGINE,
    	.port_present = true,
-		.start_logical_lane = 1,
-		.end_logical_lane = 1,
+		.start_logical_lane = 16,
+		.end_logical_lane = 19,
+		.device_number = 2,
+		.function_number = 4,
+		.link_speed_capability = GEN3,
+		.turn_off_unused_lanes = true,
+		.link_aspm = ASPM_L1,
+		.link_hotplug = 0,
+		.clk_req = CLK_REQ4,
+	},
+	{ /* WLAN */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 15,
+		.end_logical_lane = 15,
    	.device_number = 2,
    	.function_number = 2,
    	.link_speed_capability = GEN3,
    	.turn_off_unused_lanes = true,
-		.link_aspm = 2,
-		.link_hotplug = 3,
-		.clk_req = CLK_REQ1,
+		.link_aspm = ASPM_L1,
+		.link_hotplug = 0,
+		.clk_req = CLK_REQ6,
    },
-	{
+	{ /* SD */
    	.engine_type = PCIE_ENGINE,
    	.port_present = true,
-		.start_logical_lane = 2,
-		.end_logical_lane = 3,
+		.start_logical_lane = 14,
+		.end_logical_lane = 14,
    	.device_number = 2,
    	.function_number = 3,
    	.link_speed_capability = GEN3,
    	.turn_off_unused_lanes = true,
-		.link_aspm = 2,
-		.link_hotplug = 3,
-		.gpio_group_id = GPIO_27,
-		.clk_req = CLK_REQ0,
+		.link_aspm = ASPM_L1,
+		.link_hotplug = 1,
+		.clk_req = CLK_REQ5,
+	},
+	{ /* NVMe SSD1 */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 8,
+		.end_logical_lane = 9,
+		.device_number = 1,
+		.function_number = 2,
+		.link_speed_capability = GEN3,
+		.turn_off_unused_lanes = true,
+		.link_aspm = ASPM_L1,
+		.link_hotplug = 0,
+		.clk_req = CLK_REQ1,
+	},
+	{ /* GBE */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 13,
+		.end_logical_lane = 13,
+		.device_number = 2,
+		.function_number = 1,
+		.link_speed_capability = GEN3,
+		.turn_off_unused_lanes = true,
+		.link_aspm = ASPM_L1,
+		.link_hotplug = 0,
+		.clk_req = CLK_REQ3,
+	},
+	{ /* WWAN */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 12,
+		.end_logical_lane = 12,
+		.device_number = 1,
+		.function_number = 3,
+		.link_speed_capability = GEN3,
+		.turn_off_unused_lanes = true,
+		.link_aspm = ASPM_L1,
+		.link_hotplug = 0,
+		.clk_req = CLK_REQ2,
    },
 };

@@ -63,17 +112,17 @@
    	.hdp_index = DDI_HDP2
    },
    { /* DDI2 - DP (type C) */
-		.connector_type = DDI_DP,
+		.connector_type = DDI_DP_W_TYPEC,
    	.aux_index = DDI_AUX3,
    	.hdp_index = DDI_HDP3,
    },
    { /* DDI3 - DP (type C) */
-		.connector_type = DDI_DP,
+		.connector_type = DDI_DP_W_TYPEC,
    	.aux_index = DDI_AUX4,
    	.hdp_index = DDI_HDP4,
    },
-	{ /* DDI4 - unused */
-		.connector_type = DDI_UNUSED_TYPE,
+	{ /* DDI4 - DP (type C) */
+		.connector_type = DDI_DP_W_TYPEC,
    	.aux_index = DDI_AUX5,
    	.hdp_index = DDI_HDP5,
    }
@@ -98,18 +147,18 @@
    connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8;

switch (connector_type) {
-	case 0xc:
+	case 0x0c:
    	printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n");
    	return DDI_HDMI;
-		break;
    case 0x13:
    	printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n");
    	return DDI_DP;
-		break;
    case 0x14:
    	printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n");
    	return DDI_EDP;
-		break;
+	case 0x17:
+		printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n");
+		return DDI_DP_W_TYPEC;
    default:
    	printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n",
    	       connector_type);