Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Subrata Banik, Sukumar Ghorai, Tarun.
Hello Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78164?usp=email
to look at the new patch set (#5).
The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins)
Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ......................................................................
soc/intel: Fix slp-s0 residency counter frequency LPIT table
Intel platforms use Low Power Idle Table(LPIT) to enumerate platform Low Power Idle states. There are two types of low power residencies a) CPU PKG C10 - read via MSR (Function fixed hardware interface) b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped Ref. https://www.uefi.org/sites/default/files/resources/ Intel_ACPI_Low_Power_S0_Idle.pdf
System sleep time (SLP_S0 signal asserted) is measured in ticks, for MTL in 122μs granularity/ticks.
BUG=b:300440936 TEST=check kernel cpuidle sysfs for sleep residency after s0ix cycle cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us cat /sys/kernel/debug/pmc_core/slp_s0_residency_usec
Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Signed-off-by: Sukumar Ghorai sukumar.ghorai@intel.com --- M src/acpi/Kconfig M src/include/acpi/acpi.h M src/soc/intel/meteorlake/Kconfig 3 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/78164/5