Felix Singer submitted this change.

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Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved
mb/dell/snb_ivb_workst: Convert remaining PCI numbers into references

Change-Id: I9c6d931d5d5650eb5818116050f9f599a815c315
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80052
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
M src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
index bfe453f..c17593a 100644
--- a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
+++ b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
@@ -3,12 +3,12 @@
subsystemid 0x1028 0x052c inherit
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "sata_port_map" = "0x7"
- device pci 1c.4 on # PCIe Port #5
+ device ref pcie_rp5 on # PCIe Port #5
smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X"
end
- device pci 1c.5 on end # PCIe Port #6
- device pci 1c.6 on end # PCIe Port #7
- device pci 1c.7 on end # PCIe Port #8
+ device ref pcie_rp6 on end # PCIe Port #6
+ device ref pcie_rp7 on end # PCIe Port #7
+ device ref pcie_rp8 on end # PCIe Port #8
end
end
end
diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
index 81133ee..fbc21d8 100644
--- a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
+++ b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
@@ -4,16 +4,16 @@

chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "sata_port_map" = "0xf"
- device pci 1c.2 on # PCIe Port #3
+ device ref pcie_rp3 on # PCIe Port #3
smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X"
end
- device pci 1c.4 on # PCIe Port #5
+ device ref pcie_rp5 on # PCIe Port #5
smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X"
end
- device pci 1c.5 on end # PCIe Port #6
- device pci 1c.6 on end # PCIe Port #7
- device pci 1c.7 on end # PCIe Port #8
- device pci 1e.0 on # PCI bridge
+ device ref pcie_rp6 on end # PCIe Port #6
+ device ref pcie_rp7 on end # PCIe Port #7
+ device ref pcie_rp8 on end # PCIe Port #8
+ device ref pci_bridge on # PCI bridge
smbios_slot_desc "SlotTypePci" "SlotLengthLong" "SLOT3" "SlotDataBusWidth32Bit"
end
end

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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9c6d931d5d5650eb5818116050f9f599a815c315
Gerrit-Change-Number: 80052
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski@3mdeb.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: merged