[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/rauru: Initialize DPM in ramstage

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85122?usp=email )

(

8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/rauru: Initialize DPM in ramstage
......................................................................

mb/google/rauru: Initialize DPM in ramstage

Add initialization of DPM drvier for DRAM low power mode. This DPM flow
adds 3ms to the boot time, making the total boot time 860ms.

coreboot logs:
CBFS: Found 'dpm.dm' @0x19880 size 0x5b7 in mcache @0xfffdd1fc
mtk_init_mcu: Loaded (and reset) dpm.dm in 0 msecs (1888 bytes)
CBFS: Found 'dpm.pm' @0x19ec0 size 0x7fb5 in mcache @0xfffdd258
mtk_init_mcu: Loaded (and reset) dpm.pm in 3 msecs (43844 bytes)

TEST=Build pass. Check with cbmem -1.
BUG=b:317009620

Change-Id: Ib855e133a30067fc89c88d5c0fb454cc78504ff3
Signed-off-by: Crystal Guo 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85122
Reviewed-by: Yu-Ping Wu 
Reviewed-by: Yidi Lin 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/rauru/mainboard.c
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yidi Lin: Looks good to me, approved
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c
index c2d24e1..94a257f 100644
--- a/src/mainboard/google/rauru/mainboard.c
+++ b/src/mainboard/google/rauru/mainboard.c
@@ -1,8 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <console/console.h>
 #include <device/device.h>
 #include <gpio.h>
 #include <soc/bl31.h>
+#include <soc/dpm_v2.h>
 #include <soc/pcie.h>
 #include <soc/usb.h>

@@ -25,6 +27,9 @@
    setup_usb_host();
    power_on_fpmcu();

+	if (dpm_init())
+		printk(BIOS_ERR, "dpm init failed, DVFS may not work\n");
+
    if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
    	register_reset_to_bl31(GPIO_AP_EC_WARM_RST_REQ.id, true);
 }