Arthur Heymans uploaded patch set #5 to this change.
[WIP]cpu/x86/cache: CLFLUSH programs to memory before running
When cbmem is initialized in romstage and postcar placed in
the stage cache + cbmem where it is run, the assumption is made
that this are all in UC memory such that calling invd in
postcar is ok.
For performance reasons (e.g. postcar decompression) it is desirable
to cache cbmem and the stage cache during romstage. Another reason
is that AGESA sets up MTRR during romstage to cache all dram, which
is currently worked around by using additional MTRR to make that UC.
TODO be nice to reviewers and spit some parts off.
TESTED on ASUS P5QL-EM on both regular and S3 resume bootpath.
Signed-off-by: Arthur Heymans <email@example.com>
4 files changed, 74 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/37196/5
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