Felix Singer has uploaded this change for review.
intel tgl mainboards: Move PcieRpEnable option below dt entries
There is work being done on better integrating the root port entries
from the devicetree by hooking up the FSP option PcieRpEnable to them,
which supersedes the devicetree option.
Move the PcieRpEnable option below their related devicetree entries in
order to make the review easier when the option is removed. Create
devicetree entries in case of they don't exist yet.
Change-Id: I65bf27342191129b433d779774e084eecb4e4b3e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/mainboard/google/volteer/variants/chronicler/overridetree.cb
M src/mainboard/google/volteer/variants/elemi/overridetree.cb
M src/mainboard/google/volteer/variants/voema/overridetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
6 files changed, 51 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/79960/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 078deb2..e9165c7 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -113,27 +113,23 @@
register "gen3_dec" = "0x00fc0901"
# Enable NVMe PCIE 9 using clk 0
- register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[0]" = "8"
register "PcieClkSrcClkReq[0]" = "0"
register "PcieRpSlotImplemented[8]" = "1"
# Enable Optane PCIE 11 using clk 0
- register "PcieRpEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
register "HybridStorageMode" = "0"
register "PcieRpSlotImplemented[10]" = "1"
# Enable SD Card PCIE 8 using clk 3
- register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpHotPlug[7]" = "1"
register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcClkReq[3]" = "3"
# Enable WLAN PCIE 7 using clk 1
- register "PcieRpEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieClkSrcUsage[1]" = "6"
register "PcieClkSrcClkReq[1]" = "1"
@@ -470,8 +466,11 @@
device ref heci1 on end
device ref sata on end
device ref pcie_rp1 on end
- device ref pcie_rp7 on end
+ device ref pcie_rp7 on
+ register "PcieRpEnable[6]" = "1"
+ end
device ref pcie_rp8 on
+ register "PcieRpEnable[7]" = "1"
probe DB_SD SD_GL9755S
probe DB_SD SD_RTS5261
probe DB_SD SD_RTS5227S
@@ -497,8 +496,12 @@
end
end
end
- device ref pcie_rp9 on end
- device ref pcie_rp11 on end
+ device ref pcie_rp9 on
+ register "PcieRpEnable[8]" = "1"
+ end
+ device ref pcie_rp11 on
+ register "PcieRpEnable[10]" = "1"
+ end
device ref uart0 on end
device ref gspi0 on
chip drivers/spi/acpi
diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
index 28f72d7..fe5b0bb 100644
--- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb
@@ -6,7 +6,6 @@
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
# Enable EMMC PCIE 5 using clk 5
- register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[5]" = "4"
@@ -278,7 +277,9 @@
device generic 0 on end
end
end
- device ref pcie_rp5 on end
+ device ref pcie_rp5 on
+ register "PcieRpEnable[4]" = "1"
+ end
device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.
diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb
index 2152ec4..7edd297 100644
--- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb
@@ -6,7 +6,6 @@
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
# Enable EMMC PCIE 5 using clk 5
- register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[5]" = "4"
@@ -279,7 +278,9 @@
device generic 0 on end
end
end
- device ref pcie_rp5 on end
+ device ref pcie_rp5 on
+ register "PcieRpEnable[4]" = "1"
+ end
device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb
index d101b5d..90172fc 100644
--- a/src/mainboard/google/volteer/variants/voema/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb
@@ -12,13 +12,11 @@
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
# Disable WLAN PCIE 7
- register "PcieRpEnable[6]" = "0"
register "PcieRpLtrEnable[6]" = "0"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
register "PcieRpSlotImplemented[6]" = "1"
# Disable SD Card PCIE 8
- register "PcieRpEnable[7]" = "0"
register "PcieRpLtrEnable[7]" = "0"
register "PcieRpHotPlug[7]" = "0"
register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
@@ -102,6 +100,17 @@
probe AUDIO MAX98360_ALC5682I_I2S
probe AUDIO RT1011_ALC5682I_I2S
end
+ device ref pcie_rp7 off
+ register "PcieRpEnable[6]" = "0"
+ end
+ device ref pcie_rp8 off
+ register "PcieRpEnable[7]" = "0"
+ probe DB_SD SD_GL9755S
+ probe DB_SD SD_RTS5261
+ probe DB_SD SD_RTS5227S
+ probe DB_SD SD_GL9750
+ probe DB_SD SD_OZ711LV2LN
+ end
device ref pcie_rp9 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 1af05c4..506825a 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -37,10 +37,6 @@
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[8]" = "1"
- register "PcieRpEnable[10]" = "1"
register "PcieRpSlotImplemented[2]" = "1"
register "PcieRpSlotImplemented[3]" = "1"
register "PcieRpSlotImplemented[8]" = "1"
@@ -279,21 +275,28 @@
device pci 19.2 on end # UART2 0xA0C7
device pci 1c.0 off end # RP1 0xA0B8
device pci 1c.1 off end # RP2 0xA0B9
- device pci 1c.2 on end # RP3 0xA0BA
- device pci 1c.3 on
+ device pci 1c.2 on # RP3 0xA0BA
+ register "PcieRpEnable[2]" = "1"
+ end
+ device pci 1c.3 on # RP4 0xA0BB
+ register "PcieRpEnable[3]" = "1"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)"
register "srcclk_pin" = "2"
device generic 0 on end
end
- end # RP4 0xA0BB
+ end
device pci 1c.4 off end # RP5 0xA0BC
device pci 1c.5 off end # RP6 0xA0BD
device pci 1c.6 off end # RP7 0xA0BE
device pci 1c.7 off end # RP8 0xA0BF
- device pci 1d.0 on end # RP9 0xA0B0
+ device pci 1d.0 on # RP9 0xA0B0
+ register "PcieRpEnable[8]" = "1"
+ end
device pci 1d.1 off end # RP10 0xA0B1
- device pci 1d.2 on end # RP11 0xA0B2
+ device pci 1d.2 on # RP11 0xA0B2
+ register "PcieRpEnable[10]" = "1"
+ end
device pci 1d.3 off end # RP12 0xA0B3
device pci 1e.0 off end # UART0 0xA0A8
device pci 1e.1 off end # UART1 0xA0A9
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index ad1a45d..9b1177e 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -38,10 +38,6 @@
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[8]" = "1"
- register "PcieRpEnable[10]" = "1"
register "PcieRpSlotImplemented[2]" = "1"
register "PcieRpSlotImplemented[3]" = "1"
register "PcieRpSlotImplemented[8]" = "1"
@@ -283,21 +279,28 @@
device pci 19.2 on end # UART2 0xA0C7
device pci 1c.0 off end # RP1 0xA0B8
device pci 1c.1 off end # RP2 0xA0B9
- device pci 1c.2 on end # RP3 0xA0BA
- device pci 1c.3 on
+ device pci 1c.2 on # RP3 0xA0BA
+ register "PcieRpEnable[2]" = "1"
+ end
+ device pci 1c.3 on # RP4 0xA0BB
+ register "PcieRpEnable[3]" = "1"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)"
register "srcclk_pin" = "2"
device generic 0 on end
end
- end # RP4 0xA0BB
+ end
device pci 1c.4 off end # RP5 0xA0BC
device pci 1c.5 off end # RP6 0xA0BD
device pci 1c.6 off end # RP7 0xA0BE
device pci 1c.7 off end # RP8 0xA0BF
- device pci 1d.0 on end # RP9 0xA0B0
+ device pci 1d.0 on # RP9 0xA0B0
+ register "PcieRpEnable[8]" = "1"
+ end
device pci 1d.1 off end # RP10 0xA0B1
- device pci 1d.2 on end # RP11 0xA0B2
+ device pci 1d.2 on # RP11 0xA0B2
+ register "PcieRpEnable[10]" = "1"
+ end
device pci 1d.3 off end # RP12 0xA0B3
device pci 1e.0 off end # UART0 0xA0A8
device pci 1e.1 off end # UART1 0xA0A9
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