Hung-Te Lin submitted this change.
soc/mediatek: Adjust hsa, hbp, hfp packets for MIPI_DSI_MODE_LINE_END
ANX7625 requires the line packets to end at the same time.
Otherwise, the display will be shifted.
BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Jacuzzi
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I5949de1a9a1947fa188233787166a478b1de68b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
M src/soc/mediatek/common/dsi.c
M src/soc/mediatek/common/include/soc/dsi_common.h
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c
index 8254dc5..3f35443 100644
--- a/src/soc/mediatek/common/dsi.c
+++ b/src/soc/mediatek/common/dsi.c
@@ -224,6 +224,13 @@
"the panel may not work properly.\n");
}
+ if (mode_flags & MIPI_DSI_MODE_LINE_END) {
+ hsync_active_byte = DIV_ROUND_UP(hsync_active_byte, lanes) * lanes - 2;
+ hbp_byte = DIV_ROUND_UP(hbp_byte, lanes) * lanes - 2;
+ hfp_byte = DIV_ROUND_UP(hfp_byte, lanes) * lanes - 2;
+ hbp_byte -= (edid->mode.ha * bytes_per_pixel + 2) % lanes;
+ }
+
if (hfp_byte + hbp_byte < MIN_HFP_BYTE + MIN_HBP_BYTE) {
printk(BIOS_ERR, "Calculated hfp_byte and hbp_byte are too small, "
"the panel may not work properly.\n");
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index aebe62a..489a591 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -39,7 +39,9 @@
/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
/* transmit data in low power */
- MIPI_DSI_MODE_LPM = BIT(11)
+ MIPI_DSI_MODE_LPM = BIT(11),
+ /* dsi per line's data end same time on all lanes */
+ MIPI_DSI_MODE_LINE_END = BIT(12),
};
struct dsi_regs {
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